RS-485 Interface Circuit Guide (TI:SLLA036D)

Abstract: This design guide discusses how to design RS-485 interface circuits. This paper discusses the necessity of balancing transmission line standard, and gives an example of process control design. The paper also discusses the line load, signal attenuation, failure protection and current isolation.

1. Why we need to balance transmission line standards

The focus of this paper is on the most widely used balanced transmission line standard in industry: ANSI/TIA/EIA-485-A (hereinafter referred to as 485). After reviewing the key aspects of some of the 485 standards, a factory automation example shows how the differential transmission structure is implemented in the actual project.

In long-range, high-noise environments, data transmission between computer components and peripherals is often difficult and, if possible, single-ended drives and receivers are used as far as practicable. For systems that require long-distance communication, a balanced digital voltage interface is recommended.

The 485 is a balanced (differential) digital transmission line interface developed to improve the limitations of the tia/eia-232 (hereinafter referred to as 232). 485 has the following characteristics:

• High communication rates – up to 50M bits/s
• Communication distance – up to 1200 m (note: 100Kbps case)
• Differential transmission – small noise emission
• Multiple drives and receivers

In practical applications, 485 drives, receivers, or transceivers can be used if inexpensive, reliable data communication between two or more computers is required. A typical example is the use of 485 transmission information between a sales terminal and a central computer. The use of twisted pair transmission balance signal has a low noise coupling, plus 485 has a wide common-mode voltage range, so 485 allows up to 50M bit/s rate of communication, or at low speeds with a thousands of m communication distance.

Since 485 is widely used, a growing number of standards committees use the 485 standard as the physical layer specification for their communication standards. Includes ANSI SCSI (small computer system interface), Profibus standard, DIN measurement bus, and China's multifunction watt-hour Meter communication protocol standard dl/t645.

The balanced transmission line standard 485 was developed in 1983 and is used for data transmission interfaces between the host and peripherals, the clock or the control line. The standard specifies only the electrical layer, and other like protocols, timing, serial or parallel data, and the linker are all defined by the designer or higher-level protocol.

Initially, the 485 standard was defined as an upgrade to the flexibility of the TIA/EIA-422 standard (hereinafter referred to as 422). Since 422 is only simplex communication (note: 422 uses two pairs of differential communication lines, send using a pair, receive using a pair, so the data is one-way transmission on one line), 485 allows multiple drives and receivers on a pair of signal lines, facilitates half-duplex communication (see Figure 1). and 4,221 samples, 485 does not specify the maximum cable length, but in the use of 24-AWG cable, 100kbps conditions, can be transmitted 1.2km;485 also does not limit the maximum signal rate, but by the rise along the time and bit time ratio limit, which is similar to 232. In most cases, the cable length can limit the signal rate more than the driver because of the effect of the transmission line and external noise.

2. System design Considerations 2.1-wire Load

In the 485 standard, the line load takes into account the load on the line terminal and the transmission line. Whether the transmission line termination is matched depends on the system design and also on the length of the transmission line and the signal rate (in general, low-speed short distances may not be matched by the terminal).

2.1.1 Transmission line Terminal matching

Transmission lines can be divided into two models: the distributed parameter Model [1] and the lumped parameter model [2]. The test transmission line belongs to which model depends on the signal of the crossover (Rise/Fall) time TT with the drive output to the end of the cable transmission time TPD.

If the 2TPD≥TT/5, the transmission line must be processed according to the distributed parameter model, and must handle the transmission line terminal match; in other cases, the transmission line as a node parameter model, the transmission line terminal matching is not necessary.

Note 1: Distributed parametric model- voltage and current in the circuit are functions of time and are related to the geometrical dimensions and spatial position of the device.

NOTE 2: Lumped parameter model-the voltage between any two endpoints in the circuit and the current flowing into any of the device endpoints is fully determined, independent of the device geometry and spatial position.

2.1.2 Unit Load Concept

The maximum number of drives and receivers hooked up on the same 1485 communication bus depends on their load characteristics. The load on the drive and receiver is measured relative to the unit load. The 485 standard specifies that a maximum of 32 unit loads can be mounted on a transport bus.

The unit load is defined as: in a 12V common-mode voltage environment, allows 1mA current through steady load, or in the -7v common-mode voltage environment, through steady-state load 0.8mA current. The unit load may consist of a drive, receiver, and fail-safe resistor, but does not include an AC termination resistor.

Figure 2 shows an example of the SN75LBC176A transceiver Unit load calculation. Because the device integrates the drive and receiver together to form the transceiver (that is, the driver output and receiver inputs are connected to the same bus), it is difficult to obtain the drive leakage current and receiver input current separately. For ease of calculation, the receiver input impedance is treated as a k, and the transceiver is given a 1mA current. This can represent a unit load, which allows 32 of such loads on a single transport bus.

As long as the input impedance of the receiver is greater than 12k, then more than 32 such transceivers can be used on a single transport bus.

Figure 2: Unit load concept

2.2 Signal attenuation and distortion

A useful common sense is that the signal attenuation -6db is allowed under the condition of maximum signal rate (in Hz) communication. In general, the cable supplier provides a signal attenuation chart. The curve shown in Figure 3 shows the relationship between the attenuation and frequency of the 24-AWG cable.

Figure 3: Signal attenuation

The simplest way to determine the impact of random noise, jitter, and distortion on a signal is to use an eye chart. Figure 4 shows the signal distortion at the receiving end using a 20AWG twisted pair cable at 500 meters at different signal rates. As the signal rate increases further, the effect of jitter becomes more pronounced. At 1MBIT/S, the jitter is approximately 5%, while at 3.5mbit/s, the signal begins to be completely submerged and the transmission quality is severely degraded. In a real system, the maximum allowable jitter is typically less than 5%.

Figure 4:485 Signal distortion VS. Signal Rate

2.3 Fault protection and fail-safe 2.3.1 fault protection

As with any other system design, there must be a habitual consideration of the fault response, whether the fault is natural or environmental-induced. For plant control systems, it is often required to protect against extreme noise voltages. The 485 differential transmission mechanism, in particular the wide common-mode voltage range, makes 485 a certain immunity to noise. But in the face of complex and harsh environment, its immunity may be insufficient. There are several ways to provide protection, and the most efficient way to do this is through galvanic isolation, which is discussed later in this paper. Galvanic isolation provides better system-level protection, but is also more expensive. The more popular and cheaper option is to use diode protection. Using a diode method instead of galvanic isolation is a compromise that provides protection at a lower level. Examples of external diodes and internally integrated transient protection diodes are as follows:

Figure 5 shows the 485 transceiver sn75lbc176 external diodes to prevent transient glitches.

Figure 5: Input protection in a noisy environment

RT is usually the terminal matching resistor, which is equal to the cable characteristic impedance R0.

Figure 6 shows the internal integration of the transient suppression diode 485 transceiver sn75lbc184, for both the use of the full 485 function, PCB space is also limited. The sn75lbc184 is internally integrated with a protective diode that can be replaced directly with the sn75lbc176 for high-energy electrical noise environments.

Figure 6: Integrated transient voltage protection for noisy environments

2.3.2 Fail-Safe

Many 485 applications also require fail-safe protection, which is useful for application layers and needs to be carefully considered and fully understood.

In an interface system in which any number of drives/receivers share the same bus, the drive is inactive for most of the time, and this state is called the bus idle state. When the drive is idle, the drive outputs a high impedance state. When the bus is idle, the line voltage is in a floating state (that is, not sure if it is high or low). This can cause the receiver to be incorrectly triggered to be high or low (depending on the ambient noise and the last level polarity of the line float). Obviously, this situation is unwelcome. In front of the receiver need to have the relevant circuit, this uncertainty state into a known, pre-agreed level, which is called the failure protection. In addition, fail-safe protection also prevents data errors caused by short circuits.

There are many ways to achieve failure protection, including adding hardware circuitry and using software protocols. Although software protocols are more complex to implement, this is the preferred approach. But because most system designers, hardware designers prefer to use hardware to achieve the failure protection, increase the hardware circuit to achieve the failure protection is more often used.

The fail-safe circuit must provide a clear input voltage to the receiver, regardless of whether a short circuit or open circuit occurs. If the communication line environment is very bad, then the line terminal matching is also necessary.

Many manufacturers are now starting to integrate some fail-safe circuits, such as open-circuit failure protection, into the inside of the chip. Usually these additional circuits simply add a large resistance pull-up resistor at the receiver's phase input and a large resistance at the receiver's inverting end. These resistors are usually around 100kω, and these resistors and the end-matching resistor form a potential driver that can only provide a differential voltage of several mv. Therefore, this voltage (receiver critical voltage) is not sufficient to switch the receiver state. Using such an internal pull-down resistor allows the bus not to match the terminal, but it can significantly reduce the maximum signal rate and reliability.

Figure 7 shows some 485-interface universal external fail-safe circuit, each of which tries to maintain the receiver input voltage is not less than the minimum critical value and in one or more fault conditions (open, idle, short circuit), maintain a known logic state. In these circuits, the R2 represents the transmission line impedance matching resistor and becomes part of the voltage driver: a steady-state bias voltage is generated. Here, it is assumed that each receiver represents 1 units of load.

The table in the right half of Figure 7 lists some typical resistors and capacitance values, the type of failure protection provided, the number of unit loads used, and signal distortion. In the next section, the resistance values in the short-circuit failure circuit are calculated to illustrate how these resistance values can be modified for specific designs.

Figure 7: External 485 fail-safe circuit

To achieve short-circuit protection, more resistors are required. When the cable is shorted, the transmission line impedance becomes 0, and the termination resistor is shorted back. An additional resistor in series at the receiver input allows short-circuit failure protection.

The additional resistor R3 shown in Figure 8 can only be used where the driver and receiver are separated. Most of the 485 drives and receivers are now integrated on a single chip (called a transceiver) and are internally connected to the same bus, which cannot be protected with short-circuit failure. If short-circuit protection is required, either the internal integrated short-circuit-protected transceiver or a device separated from the driver and receiver, such as the sn75als180, can be selected. If a short-circuit fail-safe circuit is used in the transceiver, the resistor R3 will cause additional distortion of the output signal. The device sn75als180 the driver and receiver is not a problem because the drive is connected directly to the bus, bypassing the R3.

Figure 8: Short circuit/open circuit failure protection circuitry

The resistance values are calculated by line below. If the transmission line is shorted and the R2 is removed from the circuit, the receiver input voltage is:

vid= VCC * 2r3/(2R1 + 2r3)

For 485 applications, the standard specifies that the receiver can identify the input signal from the lowest to 200mV. So when vid> vit or vid > 200mV, it is possible to determine a known state. This is the first design constraint:

vcc* 2R3/(2R1 + 2r3) > 200mV

When the transmission line is high impedance, the receiver is affected by R1, R2, and R3, and its input voltage is:

Vid= vcc* (R2 + 2r3)/(2R1 + R2 + 2r3)

Get a second design constraint:

VCC * (R2 + 2r3)/(2R1 + R2 + 2r3) > 200mV

The transmission line is affected by the end-match resistor R2 in parallel with twice times (R1+R3). The characteristic impedance of the transmission line is matched by the Zo, which is a third design constraint:

zo= 2R2 * (R1 + R3)/(2R1 + R2 +2R3)

Other design constraints include additional line loads provided by the fail-safe circuitry, signal distortion caused by R3 and R1, and receiver input resistors.

Note: The SN75HVD10 3.3V 485 transceiver and the update product are internally integrated with a short/open circuit failure protection circuit.

2.4 Galvanic Isolation

Computer and industrial serial interfaces are often in noisy environments and may affect the integrity of data transmissions. For any interface circuit, the method tested to improve noise performance is galvanic isolation.

In a data communication system, isolation means that there is no direct current flow between multiple drives and receivers. Isolation transformers provide power to the system, and optocoupler or digital isolation devices provide data isolation. Galvanic isolation can remove the ground circulation and suppress the noise voltage. Therefore, using this technique can suppress common mode noise and reduce other radiated noise.

As an example, Figure 9 shows a node in the process control system that connects the data logger and the host computer via a 485 link.

When an adjacent motor starts, the ground potential of the data logger and the computer is different instantaneously, which usually causes a large current. If the data communication is not in isolation, the data may be lost and worse, the computer will be compromised.

2.4.1 Circuit Description

The schematic diagram shown in Figure 9 is a node of a distributed monitoring, control, and management system that is typically used for process control. The data is transmitted through a pair of twisted pairs, and the ground uses a shielding layer. These applications often require low power consumption because many remote stations use batteries or require a backup battery (a capacitor that requires a spare battery to work for a certain amount of time after a power outage). In addition, a small isolation transformer can be used with a low power count. 9, the transceiver uses SN65HVD10, of course any TI company 3.3V or 5V RS485 transceiver, 3.3-v tia/eia-644 LVDS or 3.3-v tia/eia-899 M-LVDS transceiver can use this circuit.

2.4.2 Operating principle

The example shown in Figure 9 can be used for 3.3V or 5V, the power supply is isolated using a transformer, and the data signal is isolated with a digital isolator. Since the 485 transceiver requires an isolated power supply, the adjustable Ldo regulator must be isolated. This function can be achieved with a non-gate oscillation circuit-driven isolating transformer. The output voltage of the transformer is adjusted and filtered for use by a low dropout linear regulator. In high-EMI environments, this method is often used to prevent noise coupling from other long-distance power supply subsystems to the main power supply. The TPS7101 is used to power other electronic components, providing up to 500mA of current. By adjusting the bias resistor r7,tps7101 can output 3.3V or 5V, the specific resistance see BOM list.

Data signal isolation and three-channel digital isolator iso7231m completed. The device can provide 2.5KV (RMS) voltage isolation and 50kv/us instantaneous discharge protection with a 150Mbps signal rate.

Figure 9:3.3v or 5V isolated 485 nodes (on the left is the ground plane, the right side is the isolated ground plane)

Table 1:3.3v or 5V isolated 485-node BOM list

3. Process Control Design Examples

A good way to get more 485 system design knowledge is to look at specific examples. Consider a system with a system capacity of 1 master controllers, several sub-stations of the factory automation system, each of which can send and receive data.

The system features are as follows, and the general specifications are shown in Figure 10.

• Up to 500 m from the main controller of the station
• 31 stations (plus a total of 32 units)
• Signal transmission rate is kbit/s
• Half-duplex communication

Figure 10: Example of Process Control design

According to the 485 standard equipment to transmit data at kbit/s, requires that the drive output crossover (Rise/Fall) Time TT cannot be greater than 0.3 unit intervals (UI), so there are:

tt≤0.3 * UI

tt≤0.3 * (1/($ * 103)) = 600ns

If the cable transmission signal speed is equal to the light propagation speed in the vacuum, then the signal transmission delay TPD is 3.33ns/m, multiplied by the transmission line length of 500 meters, for 1667ns.

According to the formula of section 2.1, we can determine whether the transmission line is a distributed parameter model or a node parameter model: If 2TPD≥TT/5, the transmission line is considered as the distributed parameter model. Obviously, 3334 > 120, so the transmission line model for this example is the distributed parameter model. In an industrial environment, this transmission line must be matched to the terminal.

With respect to attenuation, even though the basic frequency at which the signal rate is at kbit/s is up to + khz, we still calculate the attenuation at a range of khz, because the signal actually contains the higher-frequency part. According to the maximum attenuation does not exceed the -6db rule of thumb, requires 500 meters cable end maximum attenuation is less than -6db, that is 0.36db/30 meters. Let's look at the chart shown in Figure 3, which is a graph of the attenuation and frequency relationships provided by the cable manufacturer, with a attenuation of 0.5db/30 meters for a frequency of up to a few more, exceeding the design constraints of 0.14db/30 meters. This is permissible in this example because it is acceptable to slightly reduce the noise tolerance provided by the Conservative rule.

RS-485 Interface Circuit Guide (TI:SLLA036D)