Warning warning analysis of quartuⅱ

1. Found clock-sensitive change during active clock edge at time on register ""
Cause: the clock-sensitive signals in the vector source file (such as data, allowed ends, zeroes, and synchronous loading) change at the same time at the clock edge. however, sensitive clock signals cannot change at the clock edge. the result is that the result is incorrect.
Measure: edit the vector source file.

2. maid at: Truncated with size to Match Size of target (
Cause: In the HDL design, the number of digits of the target is set, for example, Reg [] a. The default value is 32 digits, and the number of digits is determined to the appropriate size.

Measure: if the result is correct, no correction is required. If you do not want to see this warning, you can change the set number of digits.

3. All reachable assignments to data_out (10) Assign '0', register removed by optimization
Cause: After optimization by the synthesizer, the output port no longer works.

4. Following 9 pins have nothing, Gnd, or VCC driving dataIn port -- changes to this connectivity may change fitting results
Cause: 9th feet, empty or grounded or powered on
Measure: Sometimes the output port is defined, but the output end is directly assigned '0', it will be grounded and assigned '1' power supply. if these ports are used in your design, you can ignore these warnings.

5. Found pins ing as undefined clocks and/or memory enables
Cause: Your pin as the clock has no constraint information. you can set the corresponding PIN. it mainly refers to some of your pins that play the role of the clock pin in the circuit, such as the CLK pin of flip-flop, which has no clock constraints, therefore, quartusi uses "CLK" as an undefined clock. measure: If the CLK is not a clock, you can add the "not clock" constraint. If yes, you can add it to clock setting. If the clock requirement is not high, ignore this warning or change it here: Assignments> timinganalysissettings...> individual clocks...>...

6. Timing Characteristics of device epm570t144c5 are preliminary
Cause: Because maxii is not the official version of the time sequence of the new components in quartuⅱ, we have to wait for the service pack.
Measure: only the waveform of Quartus is affected.

7. Warning: clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Measure: Change timing requirements & option --> More timing setting --> enable clock latency to off.

8. Found clock High Time violation at 14.8 ns on register "| counter | lpm_counter: count1_rtl_0 | dffs [11]"
Cause: the steup/hold time is violated. It should be post-simulation to see if the waveform settings match the steup/hold time along the clock.
Measure: Adding registers in the middle may solve the problem.

9. Warning: circuit may not operate. Detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data Delay
Cause: the clock jitter is greater than the data delay. This problem occurs when the clock is very fast, and if and other classes are too many layers. However, this problem occurs mostly at the maximum frequency of the device.
Measure: Setting --> timing requirements & options --> change default required fmax to a smaller value, for example, to 50 MHz.

10. Design contains input pin (s) that do not drive Logic
Cause: the input pin has no driver logic (other pins are driven), and all input pins need to have the input Logic
Measure: if this situation is intentional, ignore it. If it is unintentional, enter the logic drive.

11. Warning: Found clock High Time violation at 8.9ns on node 'test3. clk'
Cause: the retention time of the PLS entered in FF is too short.
Measure: set a high clock frequency in ff.

12. Warning: Found 10 node (s) in clock paths which may be acting as ripple and/or gated clocks -- node (s) analyzed as buffer (s) resulting in clock skew
Cause: if you use a CPLD with only one set of global clock, the clock generated by the global clock is processed as a signal in the wiring, and the low clock skew (Skew) cannot be guaranteed ). the timing circuit working on this clock is not reliable, and even the problems caused by each wiring are different.
Measure: If you use an FPGA chip with more than two sets of global clock, you can use the second Global clock as another clock to solve this problem.

13. Critical warning: timing requirements were not met. See report window for details.
Cause: the timing requirement is not met,
Measure: Double-click compilation report --> time analyzer --> red part (for example, clock setup: 'clk') --> left-click list path to view the fmax slack report and solve it as prompted, it may be Program Of Algorithm Problem

14. can't achieve minimum setup and hold requirement along path (s). See report window for details.
Cause: timing analysis finds that a certain number of paths violate the minimum setup and retention time, which is related to clock skew. Generally, this is caused by multiple clocks: use the compilation report --> time analyzer --> red part (such as clock hold: 'clk') to check whether the hold time is a negative value or the setup time is a negative value in slack. Then, in: assignment --> assignment editor --> Add the clock name (from
Node finder). The multicycle and multicycle hold options related to multiple clocks are added to the assignment name. If the hold time is negative, the multicycle hold value can be set to multicycle, for example, set to 2 and 1.

15: Can't analyze file -- file E: // QuartusII/*. V is missing
Cause: an attempt to compile a non-existent file may be renamed or deleted
Measure: No matter him, it has no effect.

16. Warning: Can't find signal in vector source file for Input Pin whole | clk10m
Cause: Because the vector source file does not include all input
Signal (input pin) is added, which requires an incentive source for each input.

17. Error: Can't name logic scloud O0 of instance "inst" has same name as current design File
Cause: the module name is the same as the project name.
Measure: change one of the two names. Generally, change the module name.

18. warning: using design file lpm_1_o0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_1_o0
Cause: the module is not generated in this project, but is generated by directly copying the schematic diagram of other projects and the source program, instead of adding files to this project using Quartus.

Measure: ignore it and avoid affecting usage.

19. Timing Characteristics of device are preliminary
Cause: the current version of quartuⅱ only provides initial time series feature analysis for this device
Measure: if you stick to the current device, ignore this warning. Further time series feature analysis will be improved in later versions of Quartus.

20. Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected Device Family
Cause: analyze_latches_as_synchronous_elements setting allows quaruts II to analyze synchronization locks. However, the current device does not support this feature. Ignore this feature. timing Analysis may analyze latches into loops. however, the analysis is not necessarily correct. the consequence may result in a reminder to the user: changing the design to eliminate latches

21. Warning: Found XX output pins without output Pin Load capacitance assignment (available by gucheng82)
Cause: the load capacitor is not specified for the output discipline
Measure: This function is used to estimate TCO and power consumption. You can ignore this function, or specify a load capacitor for the corresponding output pin in assignment editor to eliminate warnings.

22. Warning: found 6 node (s) in clock paths which may be acting as ripple and/or gated clocks -- node (s) analyzed as buffer (s) resulting in clock skew
Cause: When the row clock or gate clock is used, when the trigger output is used, the row clock is reported. When the combination logic output is used, the gate clock is reported.
Measure: Do not use the trigger output as a clock, and do not use the output of the combination logic as a clock. If the trigger is designed, ignore the warning.

23. Warning (10268): Maid information at lcd7106.v (63): always construct contains both blocking and non-blocking assignments
Cause: a blocking or non-blocking value is assigned to an always module at the same time.

During compilation and simulation under quartuⅱ, a bunch of warnings may appear, some of which can be ignored, and some need to be noted. Although pressing F1 can help with this warning, however, sometimes the explanation is still unclear, and everyone is working together to discuss some issues about warnings that they know and understand, so as to avoid detours.
Below are some of my collected information, some of which are my own experiences and some are from netizens. I hope I can help you a little. If there is anything wrong, please correct me. If you think it is better, please give your moderator some prestige. Thank you.

1. Found clock-sensitive change during active clock edge at time <time> on register "<Name>"
Cause: the clock-sensitive signals in the vector source file (such as data, allowed ends, zeroes, and synchronized loading) change at the same time at the clock edge. The sensitive clock signal is
It cannot change on the clock edge. The consequence is that the result is incorrect.
Measure: edit the vector source file.
2. maid at <location>: Truncated value with size <number> to Match Size of target (<number>
Cause: In the HDL design, the number of digits of the target is set, for example, Reg [] a. The default value is 32 digits, and the number of digits is determined to the appropriate size.
Measure: if the result is correct, no correction is required. If you do not want to see this warning, you can change the set number of digits.
3. All reachable assignments to data_out (10) Assign '0', register removed by optimization
Cause: After optimization by the synthesizer, the output port no longer works.
4. Following 9 pins have nothing, Gnd, or VCC driving dataIn port -- changes to this connectivity may change fitting results
Cause: 9th feet, empty or grounded or powered on
Measure: Sometimes the output port is defined, but the output end is directly assigned '0', it will be grounded and assigned '1' power supply. If these ports are used in your design, you can ignore these warnings.
5. Found pins functioning as undefined clocks and/or memory enables
Cause: Your pin as the clock has no constraint information. You can set the corresponding PIN. It mainly refers to some of your pins that play the clock pin in the circuit.
Function, such as the CLK pin of flip-flop, which has no clock constraints. Therefore, quartusi uses "CLK" as an undefined clock.
Measure: If the CLK is not a clock, you can add the "not clock" constraint. If yes, you can add it to clock setting. If the clock requirement is not high, you can ignore this warning or modify it here: Assignments> timing analysis settings...> individual clocks...>...
Note that you only need to select one clock pin in applies to node. Required fmax is generally 5% higher than the required frequency, and does not need to be too tight or too loose.
6. Timing Characteristics of device epm570t144c5 are preliminary
Cause: Because maxii is not the official version of the time sequence of the new components in quartuⅱ, it has to wait for the service pack.
Measure: only the waveform of Quartus is affected.
7. Warning: clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Measure: Change timing requirements & option --> More timing setting --> enable clock latency to off.

8. Found clock High Time violation at 14.8 ns on register "| counter | lpm_counter: count1_rtl_0 | dffs [11]"
Cause: the steup/hold time is violated. It should be post-simulation to see if the waveform settings match the steup/hold time along the clock.
Measure: Adding registers in the middle may solve the problem.
9. Warning: circuit may not operate. Detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data Delay
Cause: the clock jitter is greater than the data delay. This problem occurs when the clock is very fast, and if and other classes are too many layers. However, this problem occurs mostly at the maximum frequency of the device.
Measure: Setting --> timing requirements & options --> change default required fmax to a smaller value, for example, to 50 MHz.
10. Design contains <number> Input Pin (s) that do not drive Logic
Cause: the input pin has no driver logic (other pins are driven), and all input pins need to have the input Logic
Measure: if this situation is intentional, ignore it. If it is unintentional, enter the logic drive.
11. Warning: Found clock High Time violation at 8.9ns on node 'test3. clk'
Cause: the retention time of the PLS entered in FF is too short.
Measure: set a high clock frequency in ff.
12. Warning: Found 10 node (s) in clock paths which may be acting as ripple and/or gated clocks -- node (s) analyzed as buffer (s) resulting in clock skew
Cause: if you use a CPLD with only one set of global clock, the other clock generated by global clock is processed as a signal in the wiring, and the low clock skew (Skew) cannot be guaranteed ). The timing circuit that will work on this clock is not reliable, and even the problems caused by each wiring are different.
Measure: If you use an FPGA chip with more than two sets of global clock, you can use the second Global clock as another clock to solve this problem.
13. Critical warning: timing requirements were not met. See report window for details.
Cause: the timing requirement is not met,
Measure: Double-click compilation report --> time analyzer --> red part (for example, clock setup: 'clk') --> left-click list path to view the fmax slack report and solve it as prompted, it may be a program algorithm problem or a fmax setting problem.
14. Warning: Can't find signal in vector source file for Input Pin | whole | clk10m
Cause: at this time, because the vector source file does not add all input signals (input pin), each input requires an incentive source.
15. can't achieve minimum setup and hold requirement <text> along <number> path (s). See report window for details.
Cause: timing analysis finds that a certain number of paths violate the minimum setup and retention time, which is related to clock skew. This is generally caused by multiple clocks.
Measure: Use the compilation report --> time analyzer --> red part (for example, clock hold: 'clk') to check whether the hold time is a negative value or the setup time is a negative value in slack, then, add the clock name (from node finder) to assignment editor> to, and add the multi-clock related multicycle and multicycle hold options to assignment name, if the hold time is negative, you can set the multicycle hold value to multicycle, for example, set it to 2 and 1.
16: Can't analyze file -- file E: // QuartusII/*. V is missing
Cause: an attempt to compile a non-existent file may be renamed or deleted
Measure: No matter him, it has no effect.
17. Warning: Can't find signal in vector source file for Input Pin | whole | clk10m
Cause: Because the vector source file does not include all input signals, each input requires an incentive source.
18. Error: Can't name logic function scloud O0 of instance "inst" -- function has same name as current design File
Cause: the module name is the same as the project name.
Measure: change one of the two names. Generally, change the module name.
19. warning: using design file lpm_1_o0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_1_o0
Cause: the module is not generated in this project, but is generated by directly copying the schematic diagram of other projects and the source program, instead of adding files to this project using Quartus.
Measure: ignore it and avoid affecting usage.
20. Timing Characteristics of device <Name> are preliminary
Cause: the current version of quartuⅱ only provides initial time series feature analysis for this device
Measure: if you stick to the current device, ignore this warning. Further time series feature analysis will be improved in later versions of Quartus.
21. Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected Device Family
Cause: analyze_latches_as_synchronous_elements setting allows quaruts II to analyze synchronization locks, but the current device does not support this feature.
Measure: Ignore it. Timing Analysis may analyze latches into loops. However, the analysis is not necessarily correct. The consequence may lead to a reminder to the user: changing the design to eliminate the latches, but it is actually irrelevant.
22. Warning: Found XX output pins without output Pin Load capacitance assignment
Cause: the load capacitor is not specified for the output discipline
Solution: This function is used to estimate TCO and power consumption. You can ignore it or specify a load capacitor for the corresponding output pin in assignment editor to eliminate warnings.

 

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