For the use of bands

I. CORTEX-M3 memory mapping

The storage area at the beginning of the 1GB Space is code (code) area and SRAM area, the code area is used by the optimized I-code bus to connect, similarly, the SRAM area uses D-code bus connection, although SRAM can also be used to reprint and execute code, But doing so would have forced the CPU to take instructions through the system bus, generating additional CPU wait cycles, so running code in SRAM would be slower than running on-chip flash in the code area.

The next 0.5GB storage space is the Sisu zone, the base address of all the microcontroller's user devices is in this area, the Sisu zone and the SRAM area of the starting 1MB area can be used to achieve bit addressing using bit band technology, because STM32 all SRAM and peripherals are located in this area, so STM32 all storage areas can be used "word" or "bit" implements data manipulation for the smallest unit

Early ARM7 and ARM9 processors use "&", "|" Instruction to implement bit operations in the SRAM area or peripheral storage, which is a "read", "Modify", "write" process, so it takes a few clock cycles to implement a single bit operation, and increases the amount of code

Two. The significance of the band area

How can be like MCS51 in the middle bit operation, sbit P1.0 = p1^0; P1.1 = 1; the bit segment and the bit band alias area of the STM implement this function. Can operate SRM, peripheral I/O for bit operation,

The STM32 supports bit-band operations (Bit_band) and has two zones that implement the bit bands. One is the lowest 1MB range of the SRAM area, and the second is the minimum 1MB range of the inside and outside zones. The addresses in these two districts, in addition to being used as normal RAM, have their own "bit-band alias area", which expands each bit into a 32-bit word with the alias area. Each bit expands into a 32-bit word, which is to extend the 1M to 32M,
So:

Ram address 0x200000000 (one byte) expands to 8 32-bit words, they are: (SRAM in STM32 is still 8 bits, so any address in RAM corresponds to one byte content)
0x220000000, 0x220000004,0x220000008,0x22000000c,0x220000010,0x220000014, 0x220000018,0x22000001c

In the bit segments supported by CM3, there are two zones in which the bit segments are implemented.

One is the lowest 1MB range of the SRAM zone, 0X20000000‐0X200FFFFF (lowest 1MB in the SRAM zone);

The second is the minimum 1MB range of the inside and outside of the chip, 0X40000000‐0X400FFFFF (lowest 1MB in the Sisu zone).

Three. Bit-band Operation implementation

The CORTEX?-M3 memory image consists of two bit segments (Bit-band) areas. These two bit segments map each word in the alias memory area to a bit in the memory area of the segment, and the alias store writes a word that has the same effect as the read-write operation for the target bit of the bit segment area.
In Stm32f10xxx, the peripheral registers and SRAM are mapped to a bit segment, which allows the write and read operations of a single bit segment to be performed.
The following mapping formula shows how each word in the alias area corresponds to the corresponding bit of the bit band:
BIT_WORD_ADDR = Bit_band_base + (Byte_offset x +) + (BIT_NUMBERX4)

which
BIT_WORD_ADDR is the address of the word in the alias memory area, which maps to a target bit.
Bit_band_base is the starting address of the alias area.
Byte_offset is the ordinal of the byte in the bitmap containing the target bit
Bit_number is the target bit location (0-31)

Bit with alias area address = bit with alias Enchi address + word offset address
Word Offset address = (byte relative bit stripe offset << 5) + (number of bits << 2)

Example one:
Computes the address of the 8th-bit aliased zone in GPIOB:
Register Address = 0x40010c0c
Device bit zone base address = 0x40000000
Device bit with alias area = 0x42000000
byte offset of bit stripe = 0x400010c0c-0x40000000 = 10c0c
Word offset address = (0x10c0c << 5) + (8 << 2)
Bit with alias area address = 0x42000000 + 0x2181a0 = 0x422181a0

Example two:
The following example shows how to map the byte median in the alias area where the SRAM address is 0x20000300 2
0x22006008 = 0x22000000 + (0x300*32) + (2*4);

C Code implementation:

Convert "bit with address + bit number" to alias address macro
#define Bitband (addr, Bitnum) ((Addr & 0xf0000000) +0x2000000+ ((addr &0xfffff) <<5) + (BITNUM<<2))
Convert the address into a pointer
#define MEM_ADDR (ADDR) * ((volatile unsigned long *) (ADDR))
Mem_addr (Bitband ((u32) &crcvalue,1)) = 0x1;

Note: When you use the bit segment feature, the variables to be accessed must be defined with volatile. Because the C compiler does not know that the same bit can have two addresses. Therefore, it is necessary to pass the volatile, so that each time the compiler faithfully write the new value to the memory, and no longer for the sake of optimization, in the middle of the use of registers to manipulate the copy of the data, until the last to write back the replica.

Method One:
#define Bitband (addr, Bitnum) ((Addr & 0xf0000000) +0x2000000+ ((addr &0xfffff) <<5) + (BITNUM<<2))

#define MEM_ADDR (ADDR) * ((volatile unsigned long *) (ADDR))

#define BIT_ADDR (ADDR, Bitnum) mem_addr (Bitband (ADDR, Bitnum))

Then define: #define GPIOA_ODR_ADDR (GPIOA_BASE+12)//0x4001080c

Last action: #define PAOUT (N) bit_addr (gpioa_odr_addr,n)//output ODR save data to be output; IDR save read-in data

Test code:

/*
* Love rain test bit belt operation area Experiment
* Hardware interface: GPIOC9----LED
* Experimental phenomenon: low-level light
*/
#define MEM_ADDR (ADDR) * ((volatile unsigned long *) (ADDR))

#define Bitband (Addr,bitnum) ((addr & 0xf0000000) + 0x2000000 + ((addr & 0xfffff) << 5) + (Bitnum << 2 ))

void Main ()
{
Rcc_configuration (); System Clocks Configuration
Nvic_configuration (); NVIC Configuration
Tim2_configuration ();
Led_init ();
Led_off ();
while (1)
{
Led_prompt ();
Mem_addr (Bitband (0x4001100c,9)) = 0; LED lit
}
}

Method Two

#define __BITBAND__ __attribute__ ((Bitband))

#define __BITBAND__ADDR (ADDR) __attribute__ ((at (ADDR)))

typedef struct

{

U32 a1:1;

U32 a2:1;

} _state_flag __bitband__;

Volatile _state_flag Stateflag __bitband__addr (0x20000000);

STATEFLAG.A1 = 1;

Assembly Code Comparison:

Method three directly add "--bitband" to the C + + compiler option, then the bit variables in the struct will make

Use a bit band operation.

If you use this method, the C file does not have to be as cumbersome as described in method two. Can be directly according to the normal structure

Variable description.

volatile struct

{

U32 a1:1;

U32 a2:1;

} Stateflag;

Four. Bit Zone limitations

To enable the compiler to support bit-band operations, the code is required. Can only be used in a purely structural body, cannot be mixed with Uinon, enum. Valid for a bit in a struct, when the bits in the struct are 2 bits or more, they are compiled in the order of "read-change-write".

This article is based on a reference to information:

1> CortexM3 Technical Reference manual. pdf

2> STM32 Chinese Reference manual _v10.pdf

3> STM32 Self-study note 2012.pdf

4> MDK the bit band operation under CORTEX-M3. pdf