Forget it, so many people asked me about VGA. I still pay for it all over the world for free. It's so lazy.

Timing: http://tinyvga.com/vga-timing

Design by using OpenGL: vga_desin-> vga_display-> vga_driver layer-by-layer recursion

(1) You don't need to talk about the top layer, you know.

(2) vga_diaplay: Read the row and column values and give the color to use your imagination.

// LCD VGA interfaces are all the same
Module vga_display
(
Input CLK,
Input rst_n,

Input [8: 0] x_pos,
Input [8: 0] y_pos,
Output [:0] LCD _data
);

// Define color variable RGB--5 | 6 | 5
Parameter Red = 16 'hf800;/* 11111,000000, 00000 f800 red */
Parameter Green = 16 'h07e0;/* 00000,111111, 00000 07e0 green */
Parameter Blue = 16 'h001f;/* 00000,000000, 11111 001f blue */
Parameter white = 16 'hffff;/* 11111,111111, 11111 FFFF white */
Parameter black = 16 'h0000;/* 00000,000000, 00000 0000 black */
Parameter yellow = 16 'hffe0;/* 11111,111111, 00000 ffe0 yellow */
Parameter cyan = 16 'hf81f;/* 11111,000000, 11111 f81f green */
Parameter royal = 16 'h07ff;/* 11111, 111111, 07ff */

......

(3) vga_driver underlying driverCode, Write according to the time sequence to make it easier

/*************************************** *****************************
* Module name: vga_driver
* Author: crazy bingo
* Device: ep2c8q208c8n
* Version: Quartus II 9.1
* Date: 2011/2/15
* Description: dispaly programs for the VGA
**************************************** *****************************/
/*************************************** *****************************
* Revision Author: crazy bingo
* Date:
* Description: VS can only use an enabling clock instead of a clock. Otherwise, the overall performance is affected and data loss occurs.
Using the highest clock to control the entire system will always cause system performance degradation or even errors
**************************************** *****************************/

Module vga_driver
(
Input clk_vga, // VGA pixel clock
Input rst_n, // Asynchronous Reset Signal
 
Input [15: 0] vga_data,
Output [] vga_rgb, // receives the color to be displayed
Output Reg vga_hs, // VGA pin row Synchronization
Output Reg vga_vs, // VGA pin field synchronization
 
Output [] x_pos, // pixel abscissa
Output [] y_pos // pixel ordinate position
);

/* | Display | frontier | synchronization | Trailing Edge |
* | ____ | |____ |
*________________________________________________________
* | Display | not displayed |
*_________________________________________________________
* | Display the frame length of a row |
*/
// Define the vga_1024_768_65m_60hz display protocol standard
Parameter h_disp = 11 'd1024; // display the Time Series
Parameter h_front = 11'd24; // display the front
Parameter h_sync = 11 'd136; // synchronous pulse
Parameter h_back = 11 'd160; // display the rear edge
Parameter h_total = 11 'd1344; // time series frame length

Parameter v_disp = 10 'd768; // display the Time Series
Parameter v_front = 10'd3; // display the front
Parameter v_sync = 10'd6; // synchronous pulse
Parameter v_back = 10'd29; // display the rear edge
Parameter v_total = 10'd806; // time series frame length

// ----------------------------------------
// synchronous signal generator
Reg [] hcnt;
always @ (posedge clk_vga or negedge rst_n)
begin
If (! Rst_n)
hcnt <= 0;
else
begin
If (hcnt hcnt <= hcnt + 1 'b1;
else
hcnt <= 0;
end

always @ (posedge clk_vga or negedge rst_n)
begin
If (! Rst_n)
vga_hs <= 1;
else
begin
If (hcnt> = h_disp + H_FRONT-1) & (hcnt vga_hs <= 0;
else
vga_hs <= 1;
end

// ----------------------------------------
// field synchronous signal generator
Reg [] vcnt;
always @ (posedge clk_vga or negedge rst_n)
begin
If (! Rst_n)
vcnt <= 0;
else
begin
If (hcnt = H_DISP-1)
begin
If (vcnt vcnt <= vcnt + 1 'b1;
else
vcnt <= 0;
end

Always @ (posedge clk_vga or negedge rst_n)
Begin
If (! Rst_n)
Vga_vs <= 1;
Else
Begin
If (vcnt> = v_disp + V_FRONT-1) & (vcnt <v_disp + v_front + V_SYNC-1) // delay for one CLK
Vga_vs <= 0;
Else
Vga_vs <= 1;
End
End

//------------------------------------------
/* Define the column coordinates of h_disp * v_disp */
Assign x_pos = (hcnt Assign y_pos = (vcnt <v_disp )? Vcnt [9:0]: 10'd0;
Assign vga_rgb = (hcnt

Endmodule

I have time to write the IP address in a few days.