(Formerly known as pipeline) How can I use Pipeline Bridge to add fmax of the niosii system? (SOC) (Quartus II)

Abstract
In the DE2-70, just after a NiO II system was installed on Quartus II, almost all of us would encounter a critical warning: "Critical warning: timing requirements for slow timing model timing analysis were not met. see report window for details. ", how can we solve it?

Introduction
Use environment: Quartus II 8.1 + NiO II eds 8.1 + DE2-70 (Cyclone II ep2c70f896c6n)

James and John have recently worked hard to study the niosii system, moving from the de2 platform to a larger DE2-70 platform, but have encountered a very difficult problem, just like a systems of niosii, there will almost be a critical warning:

"No student said that the warning of Quartus II can still be ignored, but the critical warning cannot be done again, right ?』 Although the result of the last line of the niosay II attack is correct, it is always very difficult to see this critical warning.

After the synthesis of Quartus II, the time sequence cannot meet the requirements.

Xiaomei and Alibaba originally thought it was their own code problems, but the DE2-70 CD 4 contains the nioii system examples to take, in additionDe2_70_sd_card_audio_playerIn addition, critical warning exists in the other three examples.

De2_70_net

De2_70_nios_device_led

De2_70_nios_host_mouse_vga

De2_70_sd_card_audio_player (normal)

When I saw that the example of the DE2-70 CD had this problem, James and Alibaba confirmed that they were not having a problem with their own code, but they were not predictable, finally, I have to ask non-senior students.

「 No senior student, why can't I meet de2's demand in this time sequence? I also added constraint in Quartus II, hoping that Quartus II can synthesize a 100 MHz fmax system, but how can Quartus II not match the MHz I want, he called the hacker... 'The impatient alicloud raised the question first.

"DE2-70 is also difficult for me for a long time, I used de2 without such critical warning, it was not until recently that the architecture of the Pipeline Bridge and Altera's niosii high-performance example with bridges was found that the issue of the publisher was solved. 』

 

What is Pipeline Bridge? I never heard of it before ...』

"The concept of bridge was raised after Quartus II 7.1, that is, to understand the problem that fmax has been down in the system of niosii, we can see from the above, some slow Server Load balancer instances pass through the pipeline bridge and master nodes. Unlike the traditional architecture, each master has a Failover channel with the Server Load balancer. 』

"Why can fmax be added in this way ?』

"There are two main reasons :』

"1. because of the zookeeper channel, the master and slave of the same system have the largest concurrency, as long as the master does not access the same slave at the same time, however, the consistency of the system is also increased, so fmax is not high. if the system does not have a large number of concurrency requirements for slow slave, using bridge can reduce the complexity of the system and increase FMAX. 』

"2. pipeline Bridge adds the pipeline register to the message queues of aveon bus, such as address, writedata, write, read, byteenable, chipselect, burstcount, readdata, readdatavalid, and waitrequest, so you can pull up FMAX. 』 The students who have no choice have paused for a moment.

"This is only the initial solution. For more information, you can find the solution in chap.11 aveon memory-mapped bridges of chapus II handbook 8.1 Vol.4, alternatively, you can use the aveon memory-mapped bridges file. 』

The example in the paper "niosii high-performance example with bridges" uses Altera's own release. I don't know what will happen in the DE2-70 ?』 Xiaomei looked at the DE2-70, hope this method is useful in the DE2-70.

"Yes. I recently optimized my de2_70_nio 1.1 version. That is, how can I access SDRAM in a 32-bit way? (SOC) (nano II) (DE2-70) This article was changed to the frame structure proposed by niosii high-performance example with bridges, the results are very interesting. 』

"All slow slave instances have passed the Pipeline Bridge and are connected to the master node of the niosii CPU !!』

"The Final fmax bandwidth is up to 102.44 MHz, and critical warning cannot be seen either .』

"Pipeline Bridge is not used in the past. Pipeline constraint has reached 100 MHz, but Quartus II can only synthesize 68.35 MHz at the end 』

"Wow !! Even if a line of code has not been changed, fmax has changed from 68.35mhz to 102.44 MHz, which is amazing. "the alias of xiaomegao is called.

"Other examples of DE2-70 CD will be handed over to you !!』

"OK !! Without being a senior student 』

Download the complete program
De2_70_nios_12_pipeline_bridge.7z

Conclusion
Bridge is a very practical thing. Clever Use of bridge to build the entire system will help improve the overall efficiency) altera's new niosii-hand notebook: ch.6 of embedded design handbook (SOC) (niosii) also mentioned some guideline used by Bridge, and interesting people can take the lead.

See also
(Original example) how to access SDRAM in a 32-bit way? (SOC)
(Formerly known as "") A new niosii hand developed by Altera: Embedded design handbook (SOC) (niosii)

Reference
Niosii high-performance example with bridges
Aveon memory-mapped Bridges
Embedded design handbook