Fourth. Processor Architecture Learning Report

Fourth Chapter processor Architecture 4.1 Y86 instruction set architecture

Defines an instruction set architecture, such as Y86, that includes defining various state elements, instruction sets, and their encodings, a set of specifications, and exception event handling.

4.1.1 Programmer-Visible State

① programmer Visible State: Each instruction in Y86 reads or modifies portions of the processor state. The "programmer" here can be either the person who writes the program with the assembler code or the compiler that produces the machine code.

The processor state of the Y86 is similar to IA32. There are 8 program registers:%eax,%ecx,%edx,%ebx,%esi,%esp and%EBP. Each program register of the processor stores one word.

② memory, conceptually a large byte array, holds programs and data. The Y86 program uses a virtual address to refer to the memory location. Hardware and operating system software are combined to translate virtual addresses into actual or physical addresses, indicating that the data is actually stored in the storage area.

4.1.2 Y86 directive

The Y86 instruction set is basically a subset of the IA32 instruction set. It includes only four-byte integer operations, less addressing, and fewer operations. Because there are only four bytes of data, there is no ambiguity in what is called a "word".

On the left is the assembly code representation of the instruction, and the right is the byte encoding. The sink encoding format is similar to the IA32 att format.

4.1.3 Instruction Encoding

4.1.4 Y86 Anomalies

For Y86, when these anomalies are encountered, we simply let the processor out of the execution instructions.

In a more complete design, the processor typically invokes an exception handler, which is specified to handle some type of exception encountered.

4.1.5 Y86 Program 4.1.6 Details of some Y86 instructions

4.2 Logic Design and hardware control language HCL4.2.1 logic gates

4.2.2 Combination Circuit and HCl Boolean expression

Combinational circuits: A lot of logic gates make up a net, it can form a computational block.

There are two restrictions on building these nets: ① two or more logic gate outputs cannot be connected together, or they may cause conflicting signals on the line, which could lead to an illegal voltage or electrical malfunction.

② This net must be non-ring.

4.2.3-byte combination circuit and HCL integer expression

4.2.4 Collection Relationships

4.2.5 Memory and Clock

4.3 Y86 The order of implementation 4.3.1 will process the organization into stages

Here is a brief description of the phases and the actions performed during each phase:

• Fetch refers to the value of the program counter (PC), which reads the instruction bytes from the memory during the reference stage.
• Decoding: The decoding phase reads a maximum of two operands from the register file, resulting in Val a/val B.
• Execution: The arithmetic/logic unit performs an explicit operation (according to the value of Ifun), calculates the valid address of the memory reference, or increases or decreases the stack pointer. The resulting value is called the Vale
• Access: Data can be written to or read from memory during the visit
• Write back: Up to two results can be written to the memory.
• Update PC: Sets the PC to the address of the next instruction.

4.3.2 SEQ Hardware structure

Timing of the 4.3.3 seq

Implementation of 4.3.4 seq Stage

4.4 General principles of pipelining

An important feature of pipelining is the increased throughput of the system, which is the total number of customers served per unit of time, but it also slightly increases latency, which is the time required to serve a customer.

4.4.1 Calculation Line

4.4.2 detailed description of pipeline operation

Limitations of the 4.4.3 pipeline

• Division of inconsistencies
• The pipeline is too deep, but the revenue decreases.

4.4.4-line system with feedback

Fourth. Processor Architecture Learning Report