FPGA and Simulink combined real-time Loop Series--Experiment one Test

Experiment one Test experiment content

???? The test module is created in Simulink, the signal is generated by the test module, and then transmitted to the FPGA,FPGA readout before the signal is not processed back to Simulink for display. This is to test that the entire hardware is functioning properly in the ring and is familiar with the entire underlying development process.

Create a model to create a Development Board information

???? In the instruction window of MATLAB, enter the following instruction, Hdlsetuptoolpath (' ToolName ', ' Altera Quartus II ', ' toolpath ', 'C:\altera\11.0\quartus\bin\ Quartus.exe (modified to the path of the software installation).

???? Simulink menu Operation Verification Wizards, Fpga-in-the-loop (FIL) ....
or MATLAB prompt input: Filwizard.

???? Before the start of the experiment, it is necessary to configure the information of the Development Board according to the design schematic of the big watermelon Development Board, mainly to configure the clock signal and the reset signal, the communication interface of the FIL, as shown in.

???? In the board name option, select Create a new user board. The connection method uses JTAG to connect, the big Watermelon FPGA board card does not have the Ethernet, thus uses the Jtag interface.

???? In the Configuration Information window of the board, the FPGA chip information on the board is configured first, as shown in.

Set the name of the board LOGIC_BOARD,FPGA the vendor is Altera, the chip is Cyclone IV E, select the corresponding chip type Ep4c6e22c8,jtag chain location default.

???? The Jtag interface type, the frequency of the clock signal, the PIN number, the clock type, the PIN number of the reset signal, and the reset level information setting, as shown in.

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Save the configuration information of the Board and use the information file in the next experiment.

Create a Simulink model

???? In Board name Select the previously configured board information, the board name is Logic_board, select the Jtag interface, click Next.

???? Add RTL files, which are design Verilog or VHDL-designed code files, and set the file as the top-level file.

???? Choose to automatically generate IO based on the top-level files, the details of each IO in the column, the type of IO is also very important, in the future design to the main IO type is selected correctly. At the same time, the level of the power and clock enable signal of the reset signal is set. As shown in.

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???? Output signal type, here may be confused with the previous IO, in fact, the signal here is the signal from the FPGA output in the front io to Simulink, where the signal is dataout, the signal is output to simulink, the signal bit width of 8bit.

Generate the Simulink model and hardware model, output the file types and folders as shown in the folder.

???? When the information is highlighted in red, the Simulink model and the hardware model are created successfully, followed by the design of the Simulink model and verification of the hardware download.

Simulink module Design

The RTL code looks like this:

LIBRARY IEEE; Use IEEE.std_logic_1164.ALL; Use IEEE.NUMERIC_STD. All; ? ? ENTITY fil_led is Port Datain:in Std_logic_vector (7 Downto 0); Dataout:out Std_logic_vector (7 Downto 0); Clk:in std_logic; Clk_en:in std_logic; Reset:in std_logic); End entity; ? Architecture RTL of Fil_led is Begin ? Process (CLK) Begin If CLK ' event and clk= ' 1 ' Then If reset = ' 0 ' Then Dataout <= (others = ' 0 '); elsif clk_en = ' 1 ' Then Dataout <= DataIn; End If; End If; End process; ? end RTL;?

The signal generated by MATLAB is output to the FPGA via the JTAG interface and then the FPGA is transferred to MATLAB via JTAG for testing the entire loop.

Add the Sawtooth wave Generation module as shown in:

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???? Sets the parameters for the Sawtooth Wave module.

???? Add the Oscilloscope module as shown in.

Modify the Run time

Double-click the Fil_test module, download the Hardware SOF file ( Thus, the hardware model is not modified in this experiment, thus, directly select the default SOF save path, the next experiment, because the hardware model modified, so directly in the Quartus II project download ).

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Experimental phenomena

Appears after double-clicking the oscilloscope

FPGA and Simulink combined real-time Loop Series--Experiment one Test