FPGA and Simulink combined real-time loop Series--Experimental two LEDs

Experiment two LED experiment content

???? On the basis of experiment one, the test signal produced by Simulink is output to the LED lights on the FPGA Development Board, which will be modified on the generated hardware model, the signal sent to the FPGA is output to 8 LEDs, and the signal is assigned the PIN.

Create a model

???? In the instruction window of MATLAB, enter the following instruction, Hdlsetuptoolpath (' ToolName ', ' Altera Quartus II ', ' toolpath ', 'C:\altera\11.0\quartus\bin\ Quartus.exe (modified to the path of the software installation).

???? Simulink menu Operation Verification Wizards, Fpga-in-the-loop (FIL) or MATLAB prompt input: Filwizard.

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Hardware design

Since LED is output from the Development Board, it is necessary to modify the FPGA design engineering, the LED signal from the lowest level of the module mapping to the top layer to form a pin signal, and then based on the FPGA board PIN assignment for pin constraints, the final synthesis.

???? This requires the bottom RTL to map the bit-selection signal and the segment signal to the top layer, the topmost signal needs to be mapped out one layer at a time, from the bottom to the top of the order as follows: Fil_led_wrapper, Filcore, Fil_led_fil.

???? Make the following changes in the Filcore file (red Line callout).

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???? In the Fil_led_fil file, make the following changes, the red line callout.

???? The PIN configuration is configured with a script file.

???? Consolidated results

Simulink module Design

Implementation code

LIBRARY IEEE; Use IEEE.std_logic_1164.ALL; Use IEEE.NUMERIC_STD. All; ? ? ENTITY fil_led is Port Datain:in Std_logic_vector (7 Downto 0); Dataout:out Std_logic_vector (7 Downto 0); Clk:in std_logic; Clk_en:in std_logic; Reset:in std_logic); End entity; ? Architecture RTL of Fil_led is Begin ? Process (CLK) Begin If CLK ' event and clk= ' 1 ' Then If reset = ' 0 ' Then Dataout <= (others = ' 0 '); elsif clk_en = ' 1 ' Then Dataout <= DataIn; End If; End If; End process; ? end RTL;?

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The signal generated by MATLAB is output to the FPGA via the JTAG interface and then the FPGA is transferred to MATLAB via JTAG for testing the entire loop.

Modify the Run time

Download the Hardware SOF file

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Appears after double-clicking the oscilloscope

Experimental phenomena

FPGA and Simulink combined real-time loop Series--Experimental two LEDs