FPGA-based data non-blocking switching Design

FPGA-based data non-blocking switching Design

[Date:]

Source: China Power Grid Author: Bai Haibin, Lu Xiaoqing

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0 Introduction

With the development of FPGA and large-scale integrated circuits, there is a new way to implement data exchange. In this design, FPGA completes the exchange of serial data signals (TXD, RXD), and a dedicated Time Slot Switching chip completes the serial handshake line (RTS, CTS, DTR, DSR, DCD, RI). The internal hardware conflict monitoring function can automatically detect that two terminals are connected to the same channel or two channels at the same time to connect to the same terminal, and automatically remove the old connection status, create a new link. In this way, the original connection terminal enters the Idle State, ensuring seamless switching between the terminal and the channel timeline. By determining the status of the RI, it can also monitor the DCE status of the channel, determine whether there is a request for the channel, and report it to the monitor.

Technical Indicators: ① switching scale: 40 × 40 × 8; ② maximum switching establishment time: 200 μs; ③ maximum handshake line transmission latency: 125 μs; ④ maximum data transmission latency: less than 1 μs; ⑤ serial data rate: 8.192 Mbps.

1. Hardware Implementation

Under the control of the master unit, the Data Switching Matrix performs physical switching between the terminal data port and the channel data port. The switching matrix includes 40 DTE ports (including 24 DTE interfaces, 16 DTE/DCE configurable interfaces), and 40 DCE ports (including 24 DCE interfaces, 16 DTE/DCE configurable interfaces ). The data switching matrix is implemented by the data line Switching Matrix (TXD, RXD), handshake line Switching Matrix (RTS, CTS, DTR, DSR, DCD, RI) and switching control module (Single Chip Microcomputer). The switching control module manages two switching modules, namely data lines and handshakes, to operate on two modules in a row. Data Line switching is completed by programmable logic devices, and handshake line switching is completed by Time Slot Switching devices.

The data line switching module is implemented by FPGA and is implemented by a 0.3 million-door programmable logic device. Its resources have met the data line switching needs and can be expanded. The handshake line Switching Module uses the TSI (time slot interchange) chip MT90820, which has 16 pairs of data streams for sending and receiving. The maximum value is 2 048 × 2 048 channels without blocking switching. The Control Unit of the switching matrix is a general 8051 series single-chip microcomputer. CPLD_1, CPLD_2, and CPLD_3 use MAX7064, which can be connected to four serial handshake lines (the functions of CPLD_1, CPLD_2 and CPLD_3 can also be implemented using a large resource FPGA, small CPLD is used here ). Function 1.

Both FPGA and CPLD functions are implemented through the hardware description language (VHDL. FPGA provides functions such as data signal switching, transmission switching commands, and DCE channel status reading. It simulates an Intel 8-bit bus interface (connected control unit), a Motorola 16-bit bus interface (connected to the Time Slot Switching chip), and then changes the interface time sequence. The data switching status register in FPGA is consistent with all the registers in the corresponding handshake line switching chip to ensure synchronization between the data line and handshake line switching. The CPLD completes the functions of four serial handshake lines, including serial parallel conversion, frame group, DTE/DCE selection, and so on.

CPLD_1 can only connect to DTE. Each DTE's six handshaking lines (two rounds and four ends) correspond to two 8-bit registers, one sending register, and one receiving register. RST/DTR corresponds to the first two digits of the sending register, and CTS \ DSR \ DCD \ JI corresponds to the first four digits of the receiving register. When there is a synchronous signal Syn (8 kHz), each sending register is serialized to shift the output data, and the four sending registers send data cyclically at every frame, a data stream of 128x8 bits per frame (STi) is sent to the handshake line switching matrix. DTE0 to DTE3 occupy 0th to 3rd time slots in the data frame in sequence, and the rest are idle. The process of receiving data streams is the opposite. A Data Stream (STo) in a fixed frame format is sent from the handshake line Switching Matrix to the CPLD. The first four digits of the 0th to 3rd time slots are extracted from the Syn of the synchronous signal and placed in the corresponding receiving register, then, the handshake signal (CTS \ DSR \ DCD \ RI) of each DTE is matched in sequence ). This is the handshake signal sent from the channel (DCE) Port, thus realizing the exchange. Each DTE occupies a fixed time slot, and one DTE occupies one time slot in each frame. For example, DTE0 occupies 0th time slots, and so on. 2.

CPLD_2 can only be connected to DCE, and each DCE's six handshakes (4-wire and 2-pack) also correspond to two 8-bit registers. CTS \ DSR \ DCD \ RI corresponds to the first four digits of the sending register, and RST/DTR corresponds to the first two digits of the receiving register. When there is a synchronous signal Syn (8 kHz), each sending register is serialized to shift the output data, and the four sending registers send data cyclically at every frame, constitute a data stream (STi ), sent to the handshake line switching matrix. DCE0 to dc4occupy 0th to 3rd time slots in the data frame sequentially, and the rest are idle. The process of receiving data streams is the opposite. A Data Stream (STo) in a fixed frame format is sent from the handshake line Switching Matrix to the CPLD. The first four digits of the 0th to 3rd time slots are extracted from the Syn of the synchronous signal and placed in the corresponding receiving register, then, it corresponds to the handshake line signals of various DCE in sequence (RTS \ DTR ). This is the handshake signal sent from the terminal (DTE) Port, thus realizing the exchange. Each DCE occupies a fixed time slot, and one DCE occupies one time slot in each frame. For example, DCE0 occupies 0th time slots, and so on. 3.

CPLD_3 is the combination of CPLD_1 and CPLD_2 functions. The DTE can be transformed into DCE through the cross transformation of data lines and handshakes within the CPLD under the control of FPGA according to users' needs, the crossover method is similar to the common RS232 data crossover method. In this way, DTE is used as a DCE. When the DTE port is switched with other DTE ports, it must be changed to the DCE port. When the DTE port is switched with the DCE port, it will still be used as the DTE port. After determining whether it is DTE or DCE, the handshake line switching matrix can be sent according to the CPLD_1 and CPLD_2 methods.

2 software implementation

The software implementation adopts the C language for modular design, mainly including the main program unit, switching unit, query unit, interrupt unit, Active Reporting Unit and watchdog. The main program includes the Initialization Configuration of the Data Exchange Matrix and the judgment and selection of each function module. The switching unit controls the FPGA and the time slot chip to implement switching connections, removing connections, detecting conflicts, and forcing connections between ports. The interrupt unit is an interface for communication with the monitoring system. It is responsible for receiving commands sent from the monitoring system and sending information to be reported proactively. The query unit can query the status of each channel and whether the channel has requests (query whether the channel's ringing signal RI is valid ). The Active Reporting Unit refers to the report and timed report of the host to indicate whether the data exchange matrix works normally.

3 conclusion

With the above design, you can create a separate module. DTE interfaces can be connected to digital phones, digital faxes, and other data terminals; DCE interfaces can be connected to GSM and other data channels; DTE/DCE interfaces can be configured according to user needs, for example, multiple serial ports for computer expansion can communicate with DTE or DCE. This technology has the advantages of good versatility of the hardware platform, wide application range, and easy function expansion.