FPGA Debug Fiber Module

Debug fiber Interface interface with FPGA:

Due to the needs of the project, the previous period of time debugging the optical fiber interface, recording some design experience.

In the design, FPGA is used to control optical fiber module to complete the transmission of optical fiber data, FPGA uses Xilinx company's Spartan6 lx45t, because of its internal 2 GTP transceiver, can be used as a variety of communication protocol (Gigabit Ethernet, Pci-e,sata, etc.) Bridge, and Xilinx provides free IP core, design is more convenient.

First, establish an ISE project and add a GTP core, (this process can be referenced in the documentation provided by Xilinx:LogiCORE IP Spartan-6 FPGA GTP transceiver Wizard v1.11userGuide)

Select the Spartan6 GTP transceiver version 1.11, followed by the GTP core Setup,

The Spartan6 lx45t series FPGAs have 2 GTP cores, each with two separate channels, so you can choose according to your needs.

Next, the GTP rate and data protocol are configured, and many high-speed transmissions are based on the AURORA-8B10B Protocol (https://en.wikipedia.org/wiki/8b/10b_encoding), The speed and reference clock can be set according to the needs (the project fiber maximum rate 1.25Gbps),

Next is some configuration options for the protocol, which can refer to the rocketio™transceiver User Guide and Spartan-6 FPGA GTP transceivers, There are detailed descriptions of these options,

It is important to select the comma alignment in the data transfer, which is used to tell the data alignment in the transmission, and the following pages are configured by default.

Finally, the project can be opened directly after the GTP nuclear engineering, after compiling can be Modelsim simulation, simulation results generally do not appear problems.

Finally, you can modify the source code according to your own needs, in which the more critical place to note:

1, txcharisk parameter, this parameter is used to indicate whether the current data is to alignment (K28.5, that is, 0xBC), when sent to the alignment, must txcharisk=1, of course 0xBC can also be used as the actual data, as long as txcharisk= 0, the data will not be considered to be alignment;

2, the data width problem, in the setting GTP rate and protocol, pay attention to the choice of data width, if the choice of 16bits or 32bits, the data in the receiving end may be dislocation, (send 0x0102, received for 0x0201), simulation will not have problems, because in frame_ Check in the judgment, if dislocation occurs, will be corrected, but the choice of 8bits will not appear this problem, eliminating the subsequent error correction tasks;

3, constraints file problems, open GTP nuclear Engineering, you can see there are two constraint files, one is the GTP attribute, one is the top layer constraints,

INST mgt1_0t1r_i/tile0_mgt1_0t1r_i/gtpa1_dual_i Clkindc_b_0

NET "tile0_txusrclk0_i" tnm_net = "tile0_txusrclk0_i";

Timespec "ts_tile0_txusrclk0_i" = PERIOD "tile0_txusrclk0_i" 8.0;

If the designer wishes to create his own top-level file and instantiate the GTP kernel in the top-level file, it is necessary to include the top-level instantiated name on the constraint statement:

INST gtp_top_i/mgt1_0t1r_i/tile0_mgt1_0t1r_i/gtpa1_dual_i clkindc_b_0

NET " gtp_top_i/tile0_txusrclk0_i" tnm_net = "tile0_txusrclk0_i";

Timespec "ts_tile0_txusrclk0_i" = PERIOD "tile0_txusrclk0_i" 8.0;

The detailed design details refer to the 3 reference documents mentioned above. In the hardware implementation, the main need to configure the GTP differential clock, Fiber Rx, TX and GTP Rx, TX connection.

FPGA Debug Fiber Module