The FPGA design human body consists of six steps: design input, synthesis, functional simulation (pre-simulation), implementation, timing simulation (post-simulation), and configuration download. the design process is shown in step 2. The following describes the design steps.
1. design input
The design input includes three methods: Hardware Description Language (HDL), status chart, and schematic input. The HDL design method is a good method for designing Large-scale Digital Integrated Circuits today. Apart from the IEEE Standard in the format of VHDL and OpenGL, there are still dedicated languages released by FPGA manufacturers, for example, ahdl under Quartus. The description of the HDL language is strong in the state machine, control logic, and bus functions, so that the circuit described by it can be specific synthesizer (such as the FPGA Compiler II or FPGA express of Synopsys) while the schematic input features strong graphics, frugal unit, and clear functions in terms of top-level design, data path logic, and Manual Optimization circuit. In addition, in the Altera Quartus software environment, you can use momory editor to directly edit the internal memory and place the data. The commonly used method is based on the HDL language, supplemented by the schematic diagram. The hybrid design is carried out to give full play to their respective characteristics.
Generally, FPGA vendors have interfaces with third-party software to import third-party design files for processing. For example, both Quartus and the foundation can use the edif network table as the input network table for layout and wiring. After layout and wiring, the generated files can be handed over to a third party for subsequent processing.
2. Integrated Design
Synthesis means to optimize the functions of a given circuit and the constraints for implementing the circuit, such as speed, power consumption, cost, and circuit type, obtain a circuit design solution that meets the above requirements. That is to say, the integrated file is an HDL file (or a corresponding file), which is based on the description of the logical design and various constraints, the overall result is a hardware circuit implementation scheme, which must meet both the expected functions and constraints. In summary, there may be multiple solutions that meet the requirements, and the synthesizer will produce an optimal or near-optimal result. Therefore, the overall process is the optimization process of the design objectives. The final structure obtained is related to the performance of the synthesizer.
FPGA Compiler II is a complete tool for FPGA logic analysis, synthesis, and optimization. It generates optimized network table files from unoptimized network tables in the form of HDL, this includes three steps: analysis, synthesis, and optimization. The analysis uses the standard HDL syntax rules of Synopsys to analyze the HDL source files and correct syntax errors. The analysis is based on the selected FPGA structure and devices, logical synthesis of the network table files of the HDL and FPGA; the optimization is to optimize the speed and area based on the user's design constraints to generate an optimized FPGA network Table file, for FPGA layout and wiring tools, the circuit is optimized in the device library of a specific manufacturer, independent of silicon holding, but can be driven by constraints.
When FPGA Compiler II is used for design synthesis, the design source file should be imported under the current project for automatic syntax analysis, after the syntaxes are correct and the overall mode, target device, overall strength, multi-layer persistence selection, and optimization target settings are determined, integration and optimization can be performed. The two steps can be performed independently, and constraints can be specified between the two steps, such as clock determination, channel and port latency, module operator sharing, and register fan-out. If the design model is large, you can integrate it in a hierarchical manner. Integrate the lower-level modules first, and then the higher-level modules. When the higher-level module is comprehensively embedded, the lower-level module is don't touch to rationalize the design and integration process. The integrated network table can be output in edif format or in VHDL or OpenGL format, and imported into the specialized software provided by FPGA design vendors that supports third-party design input, to implement the FPGA chip. After integration, the report file can be output to list the comprehensive status and results, such as resource usage and comprehensive level information.
3. Simulation Verification
In a broad sense, design verification includes Feature and timing simulation and circuit verification. Simulation refers to the use of design software packages to perform a complete test of the design that has been implemented to simulate the actual working conditions in the physical environment. The pre-simulation refers to testing and simulating only the logic functions to see whether the implemented functions meet the requirements of the original design. The timing information is not added to the simulation process, and the hardware features of specific devices are not involved, for example, latency. After layout and wiring, extract the relevant device delay, connection delay, and other time series parameters. The simulation on this basis is called post-simulation, it is similar to the simulation of real device operation.
4. Design implementation
Implementation can be understood as the use of implementation tools to map the logic to the resources of the target device structure, determine the optimal logic layout, and select the wiring channel connecting the logic to the input and output functions for connection, and generate relevant files (such as configuration files and related reports ). The procedure is as follows.
(1) Conversion: Convert multiple design files and merge them into one design library file.
(2) ing: The logic gate in the network table is mapped into physical elements, that is, the logical design is divided into configurable logical blocks in the programmable logical array, the input and output blocks, and other resources. (3) Layout and wiring: A Layout refers to extracting the defined logic and input/output blocks from the ing and assigning them to the physical locations inside the FPGA. It is usually based on a certain advanced algorithm, for example, the minimum split, simulated annealing, and general stress direction relaxation are completed. Wiring is to use the Automatic wiring software to select a path for cabling resources and try to complete all logical connections. Because the latest design implementation tool is time series-driven, that is, timing analysis is performed on the entire signal channel during the device layout and wiring, you can use constraints to operate the wiring software, fulfill the performance requirements specified in the design. During the layout and wiring process, time sequence information can be extracted at the same time to form a report.
(4) time series extraction: generates a reverse mark file for subsequent time series simulation.
(5) configuration: generate the bit stream file required for FPGA configuration.
You can set options during implementation. Because it supports incremental design, it can repeat multiple cabling times and use the last cabling information for each cabling to make the cabling better or achieve the design goal. In the implementation process, you should set the default download mode to make subsequent bitstream downloads normal.
5. Time Series Analysis
During the design implementation process, the latency and estimated wiring latency of a designed functional block must be analyzed after ing, static timing analysis is also required for the function block delay and actual wiring delay of the actual layout and wiring. In a program, static timing analysis is the most important step in FPGA design. It allows designers to analyze all the key paths in detail and generate an ordered report, the report also contains other debugging information, such as fan-out or capacitive load of each network node. Static time series analyzer can be used to check the logic and time sequence of the design, so as to calculate the performance of each channel, identify reliable traces, and detect the combination of creation and retention time, the time series analyzer does not require users to generate Input Excitation or test vectors. Although Xilinx and Altera have time series analysis tools on FPGA Development kits, however, when they have third-party time series analysis tools, they only use FPGA design tools for layout and wiring, third-party dedicated time series analysis tools are used for time series analysis. Generally, FPGA vendors have interfaces with third-party time series analysis tools in their design environments. Synopsys's primetime is a good time series analysis tool that can achieve better results. Save the integrated network Table file as the DB format, which can be opened in the primetime environment. Use this software to view the timing of key paths or paths that designers are interested in, analyze them, and end the timing of the original design, it can increase the clock speed or reduce the renewal of key paths. Similar to the overall process, static timing analysis is also a repetitive process, which is closely linked with the layout and wiring steps. This operation is usually performed multiple times until the timing constraints are well met.
In the process of integration and time series simulation, primetime is used for time series analysis. After the design requirements are met, the final physical verification before FPGA chip casting can be performed.
6 download Verification
Download is to download the combined bit stream to a specific FPGA chip, also called chip configuration, on the premise that the function simulation and timing simulation are correct. FPGA is designed with two configuration modes: directly configured by a computer through a dedicated download cable, and automatically configured when the peripheral configuration chip is powered on. Because FPGA has the property of power loss information, you can use a cable to directly download bitstream at the initial stage of verification. If necessary, install the configuration chip (such as Xilinx xc18v series, altera's epc2 series ). There are multiple direct loading methods when using cable downloads. For example, you can use JTAG programmer, hardware programmer, and prom programmer for FPGA downloads from Xilinx, for the FPGA of Altera Company, the JTAG mode or passive serial mode can be selected. Most FPGAs support ieee jtag standards. Therefore, JTAG ports on chips are commonly used for downloading.
After downloading the bit stream file to the FPGA device, the physical test of the actual device is circuit verification. When the correct verification result is obtained, the design is proved correct. Circuit Verification is of great significance for FPGA casting.
FPGA Design Based on Multiple EDA tools
The simulation tool Modelsim works with the integrated tool FPGA Compiler II and the wiring tool Foundation series or Quartus to implement FPGA design flowchart 3.
In the design input phase, because Modelsim only supports VHDL or OpenGL, you can use a text editor to input the HDL language when multiple design input tools are used, you can also use the corresponding tools to complete input in graphics, but you must be able to export the corresponding VHDL or Tilde. The graphic HDL design tools that have emerged in recent years can receive input methods such as logical structure charts, status conversion charts, data flow charts, control flowcharts, and truth tables, these graphic formats are converted to HDL files through the configured translator. For example, Renoir of mentor graphics and Xilinx's foundation series all have design tools to translate the state conversion graph into HDL text. In this regard, the graphic interface of Summit (which has now been merged into innoveda) is highly user-friendly and the corresponding HDL format can be exported.
As shown in figure 3, Modelsim can be used for simulation. The first part is register transfer-level (RTL) simulation, this level of simulation verifies the syntax and basic functions of the design (excluding timing information). The second is the technical simulation for specific FPGA factories, this level of pseudo is a feature-level simulation conducted after and before implementation. The feature-level simulation generally verifies whether the integrated function can obtain the correct functions required by the designer; the third simulation is the door-level simulation, which is a simulation of the door-level timing. The door-level simulation reflects the actual latency caused by layout and wiring.
In the RTL simulation stage, a test bench should be established. This test bench can be simulated throughout the FPGA process (RTL level, function level, timing gate level ). The test bench not only provides test incentives and receive response information, but also can test the key functions in the HDL simulation process (such as the correctness of the output value of the computing component ). The production of the test bench can be achieved through text programming, or input using graphical tools, and then translated into the HDL format by the software, for example, you can use the HDL Bencher software to input test incentives on its good waveform input interface, which is then automatically converted to the HDL format.
In the function-level simulation stage, it is generally verified whether the synthesis is still the same as the RTL-level simulation results.
In the door-level simulation stage, function-level simulation has been performed for specific FPGA manufacturers' technologies. Therefore, you can obtain timing information in the standard extended format through layout and wiring for door-level simulation.
ModelSim of mentor graphics is a good simulation tool in the industry. It has powerful simulation functions and friendly graphical interfaces. It also has windows such as structures, signals, waveforms, processes, and data streams. After FPGA design (in the form of HDL) is input and compiled, the pre-simulation can be performed. The latest version of Modelsim se/plus 5.5 supports the Hybrid Simulation of VHDL and OpenGL. During simulation, you can write the hdincentive file or the execution group mode. The group mode is similar to the batch mode. Multiple execution commands written in the file can be executed consecutively, which is particularly effective for re-simulation or repeated execution of multiple commands. Performance Analysis and code coverage analysis can be performed during the simulation process. During code execution, performance analysis can analyze the percentage of code execution time. In this information, the designer can locate the design bottleneck and reduce the simulation time by optimizing the code. Code coverage analysis allows the designer to precisely know the position of the Code being performed on the test bench to facilitate debugging.
ModelSim is used for simulation. You need to export the network table of VHDL or HDL. This network table consists of basic units for specific FPGA Devices. These basic units include their definitions and features in the manufacturer's library provided by FPGA manufacturers, and manufacturers generally provide their own functions in the VHDL or VDL library. Therefore, to perform simulation under Modelsim, you need to set the manufacturer library information. If you use the apex20ke series of Altera, you need to set or compile the apex20ke_atoms.v (or. vhd) and apex20ke_component.v files to the corresponding library of the project. In addition to the network table, you also need to layout the standard latency file (SDF) output by wiring. To add the SDF file to the simulation, you can add it in the window interface settings or specify it through incentives. For example, you can use the parameter path to specify the $ sdf_annotate ("", top) clause to add an anti-tagline $ sdf_annotate ("", "TOP") when using Tilde HDL.
During the integration phase, RTL-level design functions should be implemented and optimized to basic devices with equal functions and unit latencies (but without timing information) using the constraints specified by the design, such as triggers and logic gates, the result is a network table with functions independent from FPGA. It does not contain timing information and can be used for subsequent layout and wiring. The edif network can be exported after FPGA Compiler II is integrated.
In the actual phase, the integrated edif network table is used for layout and wiring based on the Basic devices in FPGA. You can use the wiring tool Foundation Series to select specific devices (such as Virtex series devices) for layout and wiring, or use the wiring tool Quartus to select apex20ke series devices for layout and wiring, at the same time, the corresponding format of VHDL or OpenGL is output for simulation under ModelSim.
In today's digital system design, using a variety of EDA tools for processing, while using FPGA to quickly design a special system or as a test means has become an indispensable way of digital system design, understanding and familiarity with design bleeding should become a necessary knowledge for today's electronic engineers.
FPGA design process
