FPGA Design-UVM Verification Chapter Hello World

Here do not repeat UVM for what, do more than half a year FPGA design verification work, according to demand has been written with VHDL test procedures, recently watched a few days UVM verification methodology book, feel this is a good verification tool, now began UVM learning, So ready to use Modelsim to do a Hello world, so go to the Internet casually search the code, test, see below:

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1. ' Include ' uvm_pkg.sv
2. Module Hello_world_example;
3. Import uvm_pkg::*;
4. ' Include ' UVM_MACROS.SVH
5. Initial begin
6. ' Uvm_info ("Info1", "Hello world!", Uvm_low)
7. End
8. Endmodule:hello_world_example

Probably because the test tool used is relatively new (Modelsim SE 10.0c), it can be compiled directly, and then simulated/run, the results are as follows:

# refreshing C:\t_uvm\work.hello_world_example
# refreshing C:\t_uvm\work.uvm_pkg
# Loading SV_STD.STD
# Loading Work.uvm_pkg
# Loading Work.hello_world_example
# * * Warning: (vsim-3770) Failed to find user specified function ' Uvm_hdl_check_path '. The search list was empty.
# Using-sv_lib,-sv_root, and-sv_liblist arguments can provide a search list
# of GKFX libraries that would be used to resolve user specified functions.
# time:0 NS iteration:0 Instance:/hello_world_example File:top.sv
......
# * * Warning: (vsim-3770) Failed to find user specified function ' uvm_glob_to_re '. The search list was empty.
# Using-sv_lib,-sv_root, and-sv_liblist arguments can provide a search list
# of GKFX libraries that would be used to resolve user specified functions.
# time:0 NS iteration:0 Instance:/hello_world_example File:top.sv
# * * Fatal: (vsim-160) C:/MODELTECH_10.0C/VERILOG_SRC/UVM-1.1D/SRC/DPI/UVM_SVCMD_DPI.SVH: Null foreign function Pointer encountered when calling ' Uvm_dpi_get_next_arg_c '
# time:0 NS iteration:0 Process:/uvm_pkg/#INITIAL #619 FILE:C:/MODELTECH_10.0C/VERILOG_SRC/UVM-1.1D/SRC/DPI/UVM_SV Cmd_dpi.svh
#Fatal Error in Module uvm_pkg @ D:/MODELTECH_10.0C/VERILOG_SRC/UVM-1.1D/SRC/DPI/UVM_SVCMD_DPI.SVH Line

So in a network to check some information, has been debugging until now can be used, as follows:

1, set the environment variables (download good UVM extract to the following uvm_home directory)

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1. Set Uvm_home c:/modeltech_10.0c/verilog_src/uvm-1.1d
2. Set Model_tech C:/modeltech_10.0c/win32

2, compiled uvm_dpi dynamic link library (with the GCC-4.2.1-MINGW32VC9 compiler)

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1. C:/modeltech_10.0c/gcc-4.2.1-mingw32vc9/bin/g++.exe-g-dquesta-w-shared-bsymbolic-i $MODEL _tech/. /include $UVM _home/src/dpi/uvm_dpi.cc-o $UVM _home/lib/uvm_dpi.dll $MODEL _tech/mtipli.dll-lregex

3. Compiling hello_world_example source files

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1. Vlog +incdir+ $UVM _home/src-l mtiavm-l mtiovm-l mtiuvm-l MTIUPF c:/t_uvm/top.sv

4, simulation hello_world_example (need to call the newly compiled Uvm_dpi.dll)

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1. Vsim-c-sv_lib $UVM _home/lib/uvm_dpi work.hello_world_example

The final run results are:

At this point, Hello World finally came out.

FPGA Design-UVM Verification Chapter Hello World