FPGA development All-in-a-comprehensive

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FPGA Development 12: FPGA Practical Development Skills (7)

FPGA development of the 12: FPGA Practical Development Skills (8) (the original text is missing, turn from: FPGA development of the entire guide-engineer Innovation Design Treasure)

5.3.4 Comprehensive master secret Xst's 11 tips

Ricky Su (www.rickysu.com)

Tip 1, XST main reference: XST User Guide (ISE installation directory, xst.pdf in doc)
Tip 2, Supplementary reference: WP231-HDL Coding practices to accelerate Design performance
Tip 3, one of the special notes: Please add timing constraints to XST.

Typically we add UCF constraints to the project to specify timing requirements and PIN constraints. However, UCF constraints are used for Map,par and other implementations, and the integrated tool XST does not perceive the timing requirements of the system. Adding XCF constraints to XST is the key to achieving the highest frequency of results. The reason for this is obvious: the implementation tool can only be laid out on the basis of a comprehensive network table, while the integrated tool can adjust the comprehensive network table according to the requirements, making it easier for the implementation tool to meet the timing requirements. If you do not tell the timing target to the integrated device, it will result in our performance requirements are not reflected.

The XCF constraint syntax is similar to UCF and is described in detail in the Xst User Guide. In fact, the commonly used period, offest and UCF syntax is exactly the same, can be used directly in the XCF.

The way to add XCF constraints to a design is synthesize-xst----right---Synthesis Constraint File = specified path

Tip 4: Take a closer look at the warning in the comprehensive report. Remember to carefully review all the warning in the synthesis report and verify that it is safe to ignore. The generator error causes the tool to stop working, but warning is often ignored by the user. In fact, waning can prompt a lot of potential logic problems, such as some signal declaration, was used, but not assigned, or the synthesis found latch but not the desired results and so on.

Tip 5, one of the most common options: keep_hierarchy-Maintain levels. This is useful when the initial design is/debug. XST based on the level of synthesis, do not break the hierarchical optimization, all the register names are listed by name, UCF constraints can be very convenient to find the object to be constrained. If you select Soft, the hierarchy is maintained at the time of synthesis, and the tool breaks the hierarchy to optimize at map time, but instance's name remains.

Tip 6, common options Two: Register_duplication + max_fanout + equivalent_register_removal + resource_sharing-allows automatic copying of registers, setting maximum Fanout, Resource sharing is prohibited. Using a copy register when the timing is not satisfied usually improves some bottlenecks. Some optimizations made by the integrated device to save area may result in adverse timing, so shutting down equivalent_register_removal and resource_sharing can improve timing.

Tip 7, common options Three: Add IO buffers-Auto Insert buffer. When our design is used as the top layer, the tool is usually automatically inserted into IO buffer, and when the design needs to be inserted into another design as a module, it is necessary to disable the automatic insertion of IO buffer.

Tip 8, four common options: number of Clock buffers and buffer_type constraints: When BUFG in the composite result is not as imagined, we can solve it in the following two ways:

-Defines the type of buffer used for the signal with the buffer_type constraint. Specific usage in XST User Guide
-Manually inserting the BUFG and then setting the number of allowed BUFG, then manually inserted will have a high priority and first took up BUFG, the tool will no longer automatically plug BUFG.

Tip 9, BlackBox: Calling other well-integrated web tables requires the use of BlackBox. Blackbox is the only HDL file with port descriptions. For more Blackbox tip please refer to my blog (note: for RICKYSU's blog).

Tip 10, xst command-line mode: XST supports bulk operations with command-line mode.

The xst of the command line supports two modes:

Shell mode-Enter xst under CMD, then a command in the shell environment of XST;
Script mode-use XST-IFN script.scr under CMD to run commands within SCRIPT.SCR, or invoke the contents of SCRIPT.SCR in the XST shell with the script command. Prior to this, you will need to prepare the COMPILE_LIST.PRJ first. EDK actually calls XST using this method. For a more detailed syntax reference XST User Guide.

Tip 11: To view the integrated Web table, you can also use Planahead in addition to the RTL schematic tools and technology schematic tools that XST comes with. His ability to display/find more powerful, and he will first merge all the integrated network tables, not because of a modular pre-integrated well, not to look at the internal conditions.

5.4 Integrated and cabling issues with large-scale design

The timing performance of FPGA design is determined by the combination of physical devices, user code design and EDA software, ignoring any factor, which will have a great impact on timing performance. This section focuses on the optimal use of Xilinx physical devices and EDA software in large-scale design.

1) IO Constraint tips

Good design has to consider the skills of IO constraints. For Xilinx devices, the carry chain is vertically distributed, and the logical arrangement blocks have a direct connection between the three-state buffer lines in the horizontal direction, and the hard core units are basically column-distributed (with the shortest path in the horizontal direction), so the optimal solution is to place the I/O for the control signal at the top or bottom of the device and vertically The I/O of the data bus is placed on the left and right side of the device and is arranged horizontally, as shown in 5-16.

Figure 5-16 Best io layout for the Turing device

This IO allocation leverages the features of Xilinx FPGA chip architectures such as carry chain arrangement and block ram and hard multiplier placement. The carry chain is shown in structure 5-17. It can solve the carry-delay problem of multi-bit wide addition and multiplication from the lowest bit to the highest bit; block RAM and Hard multiplier can save a lot of logical resources and guarantee the timing, both of them in the FPGA chip is a top-down stripe distribution, so the data flow level, control flow vertical can maximize the use of the chip underlying architecture. Of course, in the actual system design, may not be able to fully achieve the above requirements, but should be as far as possible to the high-speed, multi-width signal arranged on the left and right side of the chip.

Figure 5-17 the carry chain structure of the Turing device

2) ISE Implementation tool

The integrated implementation tools in ISE have different levels of effort (Effort level) and, of course, use the highest level to improve timing performance without having to take other measures (such as imposing more advanced timing constraints, using advanced tools, or changing code), but it takes a long time to compute. For this reason, Xilinx recommends the best process 5-18 shown.

Figure 5-18 The best use strategy for the Turing implementation tool

When implementing the first pass, use global timing constraints and default implementation parameter options, and if the timing requirements are not met, try the following methods:

(1) Try to modify the code, such as the use of appropriate code style, add pipeline, etc.;

(2) Modify the comprehensive parameter options, such as optimization effort,use Synthesis Constraints file,keep hierarchy,register duplication,register balancing, etc.;

(3) Increase the level of effort to implement tools;

(4) The method of specifying path timing constraints is used in synthesis and implementation.

The implementation tool is divided into two parts, mapping (map) and layout (PAR), as well as par, and you can use the map-timing parameter option to constrain critical paths. For example: The parameter "Timing-driven Packing and Placement" gives the critical path priority timing constraints, and user constraints are passed from user Constraints File (UCF) through the translation (Translate) process to the design.

FPGA development All-in-a-comprehensive