FPGA development All--ise basic operation

Original link:

FPGA Practical Development Tips (2)

FPGA Development 12: FPGA Practical Development Skills (3)

FPGA Development 12: FPGA Practical Development Skills (4)

5.2 How to design early system planning for FPGA

Ricky Su (www.rickysu.com)

This article describes how to use tools to improve the efficiency of the method, the degree of applicability varies from person to person.

situation: in the initial system planning of FPGA design, we need to do the module partition, module interface definition and so on. In general, we initially design on paper, to a certain stage of the final may be entered in Visio and other tools to facilitate communication and review within the team. Although in the paper we can write very casually, and paper drawing inconvenient is that if you want to make some changes to a module or re-painting module, then often because the free paper left enough, and lead to take a new blank sheet of white paint again, more waste of time. For the electronic Visio, the convenience of modification is the benefit, but he is not designed to design an FPGA system, add input and output port is not so convenient, and does not automatically generate HDL files according to the defined module.

hdlquestion: Can we use better software for system planning?

Solution: The answer is yes. The following is a description of Ise 10.1 as an example:

1) Draw an empty module, define only the port-new schematic, select Tools---symbol Wizard, which defines the symbol name and Port properties. After completion, generate the SYM format symbol. If the port is a bus, it can be in the form of a (4:0).

2) Add symbol to schematic-on the schematic symbol page, select categories as the project folder, and in the symbols list you will see the newly created symbol. Add it to the schematic.

3) Repeat 1-2 steps to create all symbol and connect the port. If you need to modify the name of the line or the example alias of the module, you can select the component that needs to change the name and press right---Object Properties--fill in the desired name in the Name/instname pane.

4) To modify the symbol, you can modify it directly in the Sym file-can be added by right-click Add, Pin and so on, you can copy the existing PIN, and then change the pinname. But ISE10.1 's symbol Editor has some bugs with the add Pin. So opening this sym file in Ultraeditor may be a better way to modify it inside. The sym file format is easy to understand. Updateschematic is required after changing the Symbol port. The update dialog box automatically pops up after the point to schematic.
5) generate the HDL file for the schematic-click on the Sch file in the "Sources in Project" list and select "View HDL functional Model" in the "Process" window. This automatically generates schematic corresponding HDL files, which instantiate each of the modules above. To change the HDL file type, you can change the "Generated Simulation Language" property in the project properties.

6) generate the HDL file for Symbol-when you open a sym file, select Tools, Generate HDL Template from Symbol. You can choose to generate VHDL or Verilog files at this time.

At this point, we have generated the top-level files and the sub-module files to be developed, and we can already develop them on the basis of them. We may also encounter these problems during the development process:

1. I want to print out the blueprints-in addition to the print function that comes with ISE, you can also use Synplify Pro or planahead to print good-looking drawings. Since the code generated by the above process is comprehensive, HDL with port information is considered by the synthesis tool to be a blackbox wrapper, so we can use Ise or synplify to synthesize the code, and the integrated tool generates a better-looking integrated module diagram (RTL Schematic). In addition to the use of Ise and synplify to open these integrated network tables to produce RTL Schematic, you can also use Planahead to open the Comprehensive network table, its Schematic display more powerful.

2. I want to modify the port of some modules, and add a line to modify the module port is also required to edit the original schematic changes? This is the problem of the benevolent see of the beholder. Personally, after generating the HDL with port information, I prefer to modify the HDL------to generate the required connections in the Planahead--and print--and continue to think about writing on the printed draft--and continue to modify the process such as HDL.

5.3. Synthesis and simulation techniques

Tian Shi/Yun Chuang Studio

The use of 5.3.1 Integrated tool XST

The so-called synthesis is to translate the HDL language, schematic design input into a logical connection (grid) of the basic logic elements, such as with, or, not gate and RAM, trigger, and to optimize the generated logical connection according to the target and requirement (constraint condition), and generate the EDF file. The XST is embedded in the ISE 3 release and is constantly being perfected. In addition, because XST is the Xilinx Company's own comprehensive tool, the partial Xilinx chip unique structure has the better fusion.

After completing the input, simulation and pin assignment, it can be synthesized and implemented. In the Process Management Area double-click Synthesize-xst,5-1, you can complete the synthesis, and can give a preliminary resource consumption situation. Figure 5-2 shows the resources that the module occupies.

Figure 5-1 Design Synthesis window

Figure 5-2 Synthesis Results Report

The synthesis may have 3 kinds of results: if it is completely correct after the synthesis, there is a small green circle in front of the synthesize-xst; if there is a warning, a small yellow ring with an exclamation point appears, and if there is an error, there is a small red circle with a fork. After the synthesis is complete, you can double-click the view RTL Schematics to view the RTL structure diagram to see if the composite structure implements the circuit according to the design intent. ISE automatically calls the schematic editor ECS to browse the RTL structure. For a counter whose RTL structure is shown in Figure 5-3, the combined result conforms to the designer's intent to invoke the adder and register to complete the logic.

Figure 5-3 Post-synthesis RTL structure diagram

2. setting of comprehensive parameters

In general, when you use XST, all of the properties take the default values. In fact, XST can provide rich and flexible property configurations for different logic designs. The following is a description of the XST attribute embedded in ISE9.1. Open the design project in Ise, select "Synthesis–xst" in the process management area and right-click, pop-up screen 5-4 is shown.

Figure 5-4 Comprehensive options

As can be seen from Figure 5-4, the XST configuration page is divided into three categories, including comprehensive options (Synthesis options), HDL Options (HDL options), and Xilinx special options (Xilinx specific option). They are used to set comprehensive global targets and overall strategies, HDL hardware syntax rules, and Xilinx-specific structural attributes.

1) Comprehensive option parameters

The comprehensive parameters are shown in the configuration interface 5-4, including 8 options, as listed below:

"Optimization Goal": The goal of optimization. This parameter determines whether the integrated tool optimizes the design by area or speed as the priority principle. The area priority principle can save the logic resources inside the device, that is to use the serial logical structure as much as possible, but at the expense of the speed. The speed-first principle guarantees the overall working speed of the device, which is to use the parallel logical structure as much as possible, but it will waste a lot of logical resources inside the device, so it is at the expense of logical resources.

"Optimization Effort": Optimizer effort level. There are two options for "normal" and "high". For "Normal", the optimizer performs only normal optimization of the logical design, the result may not be the best, but the synthesis and optimization process executes faster. When "High" is selected, the optimizer iteratively optimizes and analyzes the logical design and produces the optimal synthesis and optimization results, usually in the form of performance and eventual design, and, of course, takes longer to synthesize and optimize.

"Use Synthesis Constraints file": Using the synthetic constraint files. If this option is selected, then the composite constraint file XCF valid.

"Synthesis Constraints file": Comprehensive constraint files. This option specifies the path to the XST synthetic constraint file XCF.

"Global Optimization Goal": The overall optimization goal. The properties you can select include "Allclocknets", "Inpad to
Outpad "," Offest in Before "," Offest out after "," Maximm Delay ". This parameter is valid only for FPGA devices and can be used to select between the registers set, the input pin to the register, the register to the output pin, or the input pin to the output pin
Optimization strategy.

"Generate RTL Schematic": Generates a register transfer-level view file. This parameter is used to generate an RTL view of the consolidated results.

"Write Timing Constraints": Write a timing constraint. This parameter is valid only for the FPGA and is used to set whether the timing constraints used to control synthesis in the HDL source code are passed to the NGC Web table file, which is used for layout and cabling.

"Verilog 2001": Select whether to support Verilog 2001 version.

HDL Language Options

The HDL language options are shown in Configuration interface 5-5, including 16 options, as listed below:

Figure 5-5 Configuration Interface options for HDL language Options

"FSM Encoding algorithm": Finite state machine coding algorithm. This parameter specifies how the finite state machine is encoded. Options are "Auto",
"One-hot", "Compact", "Sequential", "Gray", "Johnson", "User", "Speed1", "None" encoding, the default is "Auto" encoding mode.

Safe implementation: Adds a security mode constraint to implement a finite state machine, adding additional logic to the state machine from the invalid state
Switch to a valid state, or can only be reset to achieve, there are "Yes", "no" two choices, the default is "no".

"Case Implementation Sytle": The conditional Statement implementation type. This parameter is used to control the interpretation and inference of the XST synthesis tool Verilog
The conditional statement. The options are "none", "full", "Parallel", "Full-parallel", and the default is "none". For these four options, the difference is as follows: (1) "None", XST will retain the prototype of the conditional statement in the program, do not do any processing, (2) "full", XST that the conditional statement is complete, to avoid the creation of the latch; (3) "Parallel", XST It is considered that the branch cannot be produced in the conditional statement, and the priority encoder is not used; (4) "Full-parallel", XST that the conditional statement is complete and does not have a branch inside, and does not use a latch and a priority encoder.

"RAM Extraction": Memory extension. This parameter is valid only for the FPGA and is used to enable and disable the RAM macro interface. The default is to allow the use of the RAM macro interface.

Ram Style: The type of RAM implementation. This parameter is valid only for FPGAs and is used to choose whether to use block RAM or distributed RAM as the implementation type of RAM. The default is "Auto".

"ROM Extraction": Read-only memory extension. This parameter is valid only for FPGA and is used to enable and disallow read-only memory ROM macro interfaces. The default is to allow the ROM macro interface to be used.

"Rom Style": ROM Implementation type. This parameter is valid only for the FPGA and is used to choose whether to use block RAM or distributed RAM as the implementation and inference type of the ROM. The default is "Auto".

"Mux Extraction": multiplexer extension. This parameter is used to enable and disable the multiplexer's macro interface. Based on some of the default algorithms, for each identified multiplexing/selector, XST can create a macro and optimize it logically. You can select "Yes", "No" and "force"
, the default is "Yes".

Mux Style: The multiplexed implementation type. This parameter is used for the stomach macro Builder to select the implementation and inference of the multiplexed/selector macros type. You can select either "Auto", "MUXF", and "Muxcy" by default to "Auto".

"Decoder Extraction": Decoder extension. This parameter is used to enable and disable the Decoder macro interface, which is allowed by default.

"Priority Encoder Extraction": Precedence decoder extension. This parameter specifies whether to use the Encoder macro unit with precedence.

"Shift Register Extraction": Shift register extension. This parameter is valid only for the FPGA and is used to specify whether the shift Register macro unit is used. The default is enable.

"Logical shifter Extraction": Logical shift Register extension. This parameter is valid only for the FPGA and is used to specify whether to use a logical shift register macro unit. The default is enable.

"XOR collapsing": XOR or Logical merge mode. This parameter is valid only for the FPGA, and specifies whether to merge the cascading XOR logical units into a large, heterogeneous, or macro logical structure. The default is enable.

"Resource sharing": resource sharing. This parameter is used to specify whether to reuse some arithmetic processing modules such as adder, subtraction, add/subtract, and multipliers when xst synthesis. The default is enable. If the selection of the integrated tools is speed-first, then resource sharing is not considered.

"Multiplier Style": the multiplier Implementation type. This parameter is valid only for the FPGA and is used to specify how the macro generator uses the Multiplier macro unit. Options are "Auto", "Block", "LUT", and "Pipe_lut". The default is "Auto". The selected multiplier implementation type is related to the selected device.

2) Xilinx Special options

Xilinx Special options are used to adapt the user logic to the special structure of the Xilinx chip, not only to save resources, but also to improve the design frequency, which is shown in configuration Interface 5-6, including 10 configuration options, as listed below.

Figure 5-6 The options specified by the Turing thought

"Add I/O buffers": Insert the I/O buffer. This parameter is used to control whether the integrated module is automatically inserted into the I/O buffer. The default is auto insert.

Max Fanout: The maximum number of fans. This parameter specifies the maximum number of fans for the signal and the network cable. There is a direct relationship between the choice of fan and the performance of the design, which needs the user's reasonable choice.

"Register duplication": Register copy. This parameter is used to control whether registers are allowed to replicate. For the high fan out and the timing can not meet the requirements of the Register to replicate, you can reduce the number of buffer output and logic series, change some characteristics of the timing, improve the design of the operating frequency. The default is to allow register replication.

"Equivalent register removal": equivalent register Delete. This parameter is used to specify whether to remove registers that are equivalent to the register transfer-level function, which reduces the use of register resources. If a register is specified with Xilinx's hardware primitive, it will not be deleted. The default is enable.

"Register balancing": Register trim. This parameter is valid only for the FPGA and is used to specify whether the balance register is allowed. The available options are "No", "Yes", "Forward" and "backward". With the register trimming technique, the timing conditions of some designs can be improved. where "Forward"
For the forward register trim, the "backward" is the back-shift register trim. With register trim, the number of registers used will be increased or decreased accordingly. The default register is not flat.

Move first flip-flop stage: Moves the pre-level register. This parameter is valid only for the FPGA, and is used to control whether the pre-level registers are allowed to be moved during register matching. If "Register balancing" is set to "No", then the setting of this parameter is invalid.

"Move last Flip-flop Stage": Moves the post-level register. This parameter is valid only for the FPGA and is used to control whether the post-level register is allowed to be moved when the register is in use. If "Register balancing" is set to "No", then the setting of this parameter is invalid.

"Pack I/O registers into Iobs": I/O registers are placed in the input and output blocks. This parameter is valid only for the FPGA, and is used to control whether the register in the logical design is implemented with the IOB internal register. There are input and output registers in the IOB of the Turing series FPGAs. If the first or last level registers in the design are implemented with the IOB internal registers, the path between the IO pins to the registers can be shortened, which usually shortens the transmission delay of approximately 1~2ns. The default is "Auto".

"Slice Packing": optimizes the Slice structure. This parameter is valid only for the FPGA to control whether the lookup table logic of the critical path is configured as much as possible in the same slice or CLB module, thereby shortening the routing between the Lut. This function is useful for improving the working frequency of the design and improving the timing characteristics. The default is to allow optimization of the slice structure.

"Optimize instantiated Primitives": optimizes primitives that have been instantiated. This parameter controls whether primitives that have been instantiated in HDL code need to be optimized. The default is no optimization.

After the code is written, the test platform is used to verify that the module being designed meets the requirements. ISE provides two ways to build a test platform, one that uses the HDL bencher for graphical waveform editing, and the other is to use the HDL language, which is simpler and more powerful than the former. Here's how to build a test platform based on the Verilog language.

First, in the Engineering management area, set "Sources for" to behavioral Simulation, right-click anywhere, and select the "New Source" command from the pop-up menu, and then select the "Verilog Test Fixture" type, Enter the file name "Test_test" and click "Next" to go to the next page. At this point, the name of all Verilog modules in the project will be displayed, and the designer will need to select the module to be tested.

Select test with the mouse, click "Next" to go to the next page, directly click on the "Finish" button, ISE will automatically display the code in the source code editing area of the module:

' Timescale 1ns/1ps
Module Test_test_v;
Inputs
Reg CLK;
reg [7:0] din;
Outputs
Wire [7:0] dout;
Instantiate the Unit under Test (UUT)
Test Uut (
. CLK (CLK),
. Din (DIN),
. Dout (Dout)
);
Initial begin
Initialize Inputs
CLK = 0;
DIN = 0;
WAIT, NS for global, reset to finish
#100;
ADD stimulus here
End
Endmodule

This shows that ISE automatically generates the complete architecture of the test platform, including required signals, port declarations, and module invocation completion. The work required is to add the test vector generation code after the "//Add stimulus Here" in the Initial...end module. Add the following test code:

Forever begin
#5;
CLK =!CLK;
if (CLK = = 1)
din = din + 1;
Else
din = DIN;
End

After the test platform is completed. In the Engineering management area, set the "Sources for" option to behavioral Simulation, which shows the process associated with the simulation in the process management area, as shown in 5-7.

Figure 5-7 Simulation Process

Select the simulate behavioral Model under Xilinx ISE Simulator in Figure 5-7, click the right mouse button, select the properties of the pop-up menu, the Property Settings dialog box shown in 5-8, the last row of the simulation Run time is the set of simulation times and can be modified to any length, this example takes the default value.

Figure 5-8 Simulation Property Settings dialog box

After the simulation parameters are set up, you can simulate, directly double-click on the ISE Simulator software simulate behavioral Model, ISE will automatically start the Ise Simulator software, and get 5-9 simulation results shown, From there, you can see that the design achieves the expected goal.

Figure 5-9 Test Module simulation Results

FPGA development All--ise basic operation