FPGA development--timing constraints

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5.3.3 and FPGA interface-related settings and timing analysis
5.3.3.1 Adding a timing constraint using a constraint file

Generally speaking, the principle of adding a constraint is to append the global constraint, then add the local constraints, and the local constraints are relatively loose. The goal is to loosen constraints wherever possible, improve routing success probabilities, and reduce ISE layout and cabling time. Typical global constraints include periodic constraints and offset constraints. When adding global timing constraints, you need to divide different clock domains according to the clock frequency, add their periodic constraints, and then add an offset constraint to the input-output port signal, adding additional constraints to the on-chip logic.

1. Periodic constraints

Periodic constraints are the basic timing constraints attached to the clock network to ensure that the timing of all synchronization components within the clock area satisfies the requirements. In the analysis of Time series, the periodic constraint can automatically handle the inverse of the register clock end, if the adjacent synchronization element clock phase opposite, then its delay will be automatically limited to half of the period constraint value, which is actually equivalent to reduce the clock period constraints of the value, so in practice, generally do not use both the rising and falling edge of the clock signal.

The maximum frequency at which a hardware design circuit can work depends on the intrinsic settling time of the internal components of the chip, as well as the logic and routing delays between the synchronization elements. Therefore, the maximum frequency of the circuit is determined by the two parts of the code and the chip, the same procedure, the high speed of the chip can achieve a higher maximum operating frequency; Similarly, in the same chip, the speed-optimized code has a higher operating frequency, in practice often take both balance.

Before adding the clock cycle, it is necessary to have a reasonable estimate of the expected clock cycle of the circuit, so as not to attach too loose or too tight periodic constraints, too loose constraints can not meet the performance requirements, too tight constraints will increase the difficulty of layout and cabling, the results of the implementation is not necessarily ideal. The common engineering strategy is that the time limit of the additional clock period is 90% of the expected value, that is, the maximum frequency of the constraint is about 110% of the actual operating frequency.

There are two methods for additional clock cycle constraints: One is the simple method, the other is the recommended method. The easy way is to attach the periodic constraint directly to the Register clock cable, with the syntax as follows:

[Constraint signal] PERIOD = {Period length} {High | Low} [pulse duration]; where content in [] is optional, content in {} is required, "|" Represents the selection. [constrained signal] can be "Net net_name" or "Timegrp group_name", the former indicates that the periodic constraints on the network driven by the synchronization element, which is constrained to the timegrp defined by the signal packet (such as triggers, latches and RAM, etc.). {Period Length} is the required clock cycle, with units such as MS, S, NS, and PS, the default is NS, and the units are case insensitive. {High | Low} is used to specify whether the first pulse in the period is a high-level or a lower one. [Pulse duration] is used to specify the duration of the first pulse, the MS, S, NS, and PS units, and the default value is NS, which defaults to a duty ratio of 50% if the item is defaulted. such as statements:

Net "Clk_100mhz" period = 10ns high 5ns;

The period of the signal Clk_100mhz is specified to be 10ns, and the duration of the high level is 5ns, and the constraint is added to the component driven by the signal clk_100mhz.

The recommended method is often used to constrain a clock network with a complex derivation, with the following basic syntax:

Timespec "Ts_identifier" = PERIOD "tnm_reference" {Period length}

{High | Low} [pulse duration];

Among them, Timespec is a basic timing-dependent constraint used to flag timing specifications. "Ts_identifier" is represented by the keyword TS and user-defined identifier, which together form a timing specification called TS attribute definition that can be arbitrarily referenced in the constraint file, greatly enriching the definition of the derived clock. When using, first define the clock grouping, and then add the appropriate constraints, such as:

NET "Clk_50mhz" = "SYN_CLK";

Timespect "TS_SYN_CLK" = PERIOD "SYN_CLK" Hign 10;

Timespec The syntax for defining derived clocks with identifiers is:

Timespec "Ts_identifier2" = PERIOD "Timegroup_name" "Ts_identifier1"

[* |/] multiplier factor [+|-] phasevalue [unit]

Wherein, TS_IDENTIFIER2 is to derive the defined clock, Ts_identifier1 is the defined clock, "multiplier factor" is used to give a multiple relationship between the periods, Phasevalue gives the phase relationship between the two. Such as:

Define the system clock Clk_syn:

Timespec "Clk_syn" = PERIOD "CLK" 5NS;

The inverse clock clk_syn_180 and the 2-way clock clk_syn_half are given below:

Timespec "clk_syn_180" = PERIOD "clk_180" Clk_syn PHASE + 2.5ns;

Timespec "clk_syn_180" = PERIOD "Clk_half" CLK_SYN/2;

2. Offset constraint

The offset constraint is also a class of basic timing constraints that specify the relative timing relationship between the external clock and the data input and output pins and can be used only for port signals and not for internal signals, including Offset_in_before,offset_in_after,offset_out_ Before,offset_out_ 4 Basic constraints such as after. The basic syntax for an offset constraint is:

OFFSET = [in | Out] "Offset_time" [units] {before | After} "Clk_name"

[Timegrp "group_name"];

where [in | Out] Indicates whether the constraint is input or output. "Offset_time" is the time difference between the data and the valid clock edge, {before| After} Indicates whether the time difference is before or after the valid clock, "Clk_name" is the name of a valid clock, [TIMEGRP "Group_name"] is a packet signal added by the user, and by default, all the triggers driven by the clock clk_name. The offset constraint notifies the layout router of the arrival time of the input data, which can accurately adjust the layout and routing process, so that the constraint signal settling time satisfies the requirements.

1) "Offset in" offset constraint

The "offset in" offset constraint is an input offset constraint, with Offset_in_after and Offset_in_before Two, which defines how long the input data can reach the input pin of the chip after the effective clock arrives, which gives the chip's internal delay limit, The combination logic that is connected to the input pin is then constrained, and the latter defines how much time is ahead of the corresponding effective clock along with the maximum delay of the combined logic connected to it, otherwise the data is unstable when the clock comes along and the sampling error occurs. The input offset is shown in timing relationship 5-10.

Figure 5-10 Timing relationships for input offsets

For example:

NET "data_in" OFFSET = in 10.0 before "Clk_50mhz";

Indicates that the input signal data_in must reach the data input pin before the Clk_50mhz rising edge of the clock signal reaches the 10ns.

NET "data_in" OFFSET = in 10.0 after "Clk_50mhz";

Indicates that the input signal data_in must reach the data input pin within 10ns after the Clk_50mhz rising edge of the clock signal is reached.

2) "Offset out" offset constraint

The "offset out" offset constraint is an output offset constraint, with Offset_out_after and Offset_out_before Two, which defines how long the output data stabilizes after the effective clock edge, which is the upper limit of the internal output delay of the chip. The latter defines how long the data must be output before the next clock signal arrives, which is the upper limit of the logical settling time for the next level. The timing relationship of the output offset is shown in 5.3.11.

Figure 5-11 Timing relationship of output offsets

For example:

NET "Data_out" OFFSET = out 10.0 before "Clk_50mhz";

Indicates that the output signal data_out signal must leave the data output pin before the Clk_50mhz rising edge of the clock signal reaches the 10ns.

NET "Data_out" OFFSET = out 10.0 after "Clk_50mhz";

Indicates that the output signal data_out signal must remain on the data output pin in the 10ns after the Clk_50mhz rising edge of the clock signal is reached.

3. grouping constraints

Group constraints can effectively manage a large number of triggers, registers and memory units, divided into different groups, each group attached to their own constraints, in large-scale design has a wide range of applications.

1) tnm/tnm_net constraints

The tnm/tnm_net constraint is used to select a component that can form a grouping, rename it, and then add the constraint as a whole. In addition to IBUFG and BUFG, all FPGA internal components can be named with TNM, with the following grammatical rules:

{net| Inst| PIN} "ob_name" TNM = "new_name";

where "Ob_name" is the name of net, INST, and PIN, New_name is the name of the group. For example:

INST ff1 TNM = my_ff1;
NIST ff2 TNM = my_ff1;

Add the instance ff1 and FF2 to the new grouping my_ff1.

In addition, the TNM syntax also supports wildcard characters "? "and" * "improves the efficiency of adding grouping constraints to large-scale designs.

When the TNM constraint is attached to the online network, all the synchronization elements on that path are added to the grouping, but not through the IBUFG component;

When the TNM constraint is attached to the pin of a macro or primitive, all synchronized components driven by that pin are added to the new grouping, and when the TNM constraint is attached to the primitive or macro, the primitive or macro is added to the new grouping.

Tnm_net constraints are specifically used to complete the grouping of network cables, unlike TNM, where TNM can traverse IBUFG/BUFG. Therefore, if you add a TNM constraint to a port, you can define only that port, and if you add tnm_net to the port, you can traverse BUFG, and all components driven by that port will be added to the group.

2) TIMEGRP constraints

TIMEGRP is used to group merges and splits, forming a new grouping of multiple groupings. The syntax for its merge grouping is:

Timegrp "New_group" = "Old_group1" "old_group2" ...;
Among them, New_group is the new grouping, while Old_group1 and old_group2 as well ... is the existing grouping to be merged.

The syntax for splitting a grouping is:

Timegrp "New_group" = "Old_group1" EXCEPT "old_group2";
Where Old_group2 is a subset of Old_group1, New_group removes all parts of old_group2 from Old_group1.

3) Tpsync constraints

The Tpsync is used to define components that are not pins and synchronous components as synchronous components so that any point can be used as the end point and starting point of the timing specification. Its corresponding syntax is:

{net| Inst| PIN} "Ob_name" tpsync= "New_part";

The Tpsync constraint is attached to the network cable, the driving source of the network cable is the synchronization point, attached to the output pin of the synchronization component, the source of the driver of the synchronization element is the synchronization point, the output pin is the synchronization point, and is attached to the synchronization element, and the PIN is defined as the synchronization point at the input pin.

4) Tpthru constraints

Tpthru is used to define the key points on a path or set of paths, allowing the user to define any desired path. Its corresponding syntax is:

{net| Inst| PIN} "ob_name" Tpthru = "new_name";

For example, in the scenario shown in Figure 5-12, there are two paths from A1 to A2, where the latency of logic 1 is large and needs to be extracted to complete a specific constraint:

Figure 5-12 Tpthru Constraint Example Scenario

INST "A1" TNM = "S";
INST "A2" TNM = "E";
NET "a1toa2_1" tpthru = "M";
Timespec "SME" = from "S" THRU "M" to "B" 10;

The third sentence uses Tpthru to define the middle point "M", then the 4th sentence defines the whole path through M point, and selects the desired path from two parallel paths.

4. Local constraints

Local constraints include from_to constraints, maximum delay constraints, maximum offset constraints, spurious paths, system clock jitter constraints, multi-cycle paths, and multi-clock domain constraints. In practical development, as the frontier of this chapter describes, timing is designed rather than constrained automatically, so there is no more discussion of local constraints.

5.3.3.2 ways to improve timing performance

Timing performance is one of the most important indicators of FPGA design. There are many root causes for poor timing performance, but the direct causes can be divided into three categories:

Poor layout, too many logic levels, and too high a signal fan. The following is an example of timing analysis to locate the cause and give the corresponding solution.

1. Poor layout and solution

The timing report shown in Figure 5-13, where the additional perimeter constraint is 3ns, the actual period is 3.027ns, the logic time is only 0.869ns, and the wiring delay to reach 2.203ns, it is obvious that the failure is due to poor layout.

Figure 5-13 Timing report with poor layout

The corresponding solutions are:

1) The effort to adjust the layout in the ISE Layout tool (effort level);

2) Use the special effort level (extra effort) or MPPR option of the layout cabling tool;

3) If the user is familiar with area constraints, the design is re-laid out using Floorplanner relative area constraints (Rloc).

2. Excessive logical progression and solutions

In FPGA design, the higher the logic series, the higher the utilization of resources, but the greater the influence on the design work frequency. In the example shown in Figure 5-5, the additional perimeter constraint is 3ns, the actual period is 3.205ns, and the logic time is 1.307ns, which has caused a certain impact on the actual performance of the design. In this case, the ISE implementation tool has no improvement and must improve performance by modifying the code, the corresponding solution is:

1) using pipelining technology, inserting registers in the combinational logic, simplifying the original logical structure;

2) Check if the path is a multi-cycle path, and if so, add the appropriate multi-periodic constraint;

3) Good coding habits, do not nest if statements or if, case statements, and try to use case statements instead of if statements.

Figure 5-14 Timing report with too many logical series

3. High signal fan out and solution

A high fan-out causes the signal transmission path to be too long, which reduces timing performance. 5-15, the additional period constraint is 3ns, and the actual period is 3.927ns, wherein the fan out of the network cable is up to 187, resulting in cabling minimization to 3.003ns, accounting for the actual delay of 77.64%. This situation is not tolerated by any design.

Figure 5-15 fan out too high timing report

The corresponding solutions are:

1) by means of logical replication to reduce the high fan out of the signal, can be manually copied in the HDL code or through the integrated tool set to achieve the purpose;

2) You can use the zone constraints to put the relevant logic together, of course this method is limited to advanced users.

FPGA development--timing constraints