FPGA Entry Example 1: lfsr

I. task:

Hardware Logic Design of Linear Feedback Shift Register (lfsr) is required on Xilinx Virtex-6 board by using the language of Xilinx.

Ii. preparations:

Basically, the following software is required to complete a simple design:

Logic: uedit32 (recommended for hardware dogs)

Overall: ise14.1

Simulation: Modelsim se 10.1b

Analysis: chipscope pro

Iii. Design Process

Logic:

First of all, it is RTL-level design, commonly known as hardware logic design. The use of uedit32, this software is equivalent to a notepad, but the editing function is very powerful, it is simply the magic tool to write the code, download and install the specific, the use of skills for details (http://blog.163.com/bubble_fish/blog/static/23724712920146180178713 ). After learning about the convenience and efficiency of uedit32, before writing code, I would like to give you some notes. Those who have worked at work must know that the company emphasizes code writing standards, especially for large designs. If you do not follow the standards, debugging will find errors after one month, and you can look back at the code you have written. It is estimated that many signals have been forgotten, let alone check for errors; if half of a project leaves the company, the successor is estimated to have to design it from the ground up. If a new feature is added to the original version, it is likely to start from scratch, it is difficult to make the design reusable. Here is a team lead in my first day internship I will give to me to write code, to share with you, I really hope that I like the white carefully read before writing code (http://blog.163.com/bubble_fish/blog/static/237247129201461692652979 ). After understanding the writing specifications, we will analyze the tasks. For the working principle and application of Linear Feedback Shift Register (lfsr), see blog (http://blog.sina.com.cn/s/blog_62d9edac01015lsd.html ). The following is the source code of the Tilde:

1 module lfsr 2 (3 input usr_clk, // clock 4 input rst, // reset 5 output Reg [2: 0] dout // data_out 6 ); 7 8 parameter init = 3'h1; // Initial Value 9 parameter coff = 3'h4; // generate polynomial 10 11 Reg [] dout_next; 12 always @ (posedge usr_clk or posedge RST) 13 if (RST) dout <= Init; 14 else dout <= dout_next; 15 16 integer I; 17 always @(*) 18 begin19 dout_next [0] <= dout [2]; 20 for (I = 1; I <3; I = I + 1) 21 if (coff [3-I]) dout_next [I] <= dout [I-1] ^ dout [2]; 22 else dout_next [I] <= dout [I-1]; 23 end24 25 endmodule

Overall:

For Xilinx development boards, ISE is used as a comprehensive tool. The usage of the software is not described. Only one attachment is provided here, including all the engineering documents and. UCF user constraints (http://download.csdn.net/download/yuzeren48/7644573 ).

Figure 1: Comprehensive Interface

According to the lfsr working principle and the custom coff (3'b100) parameter, we can see that the entire lfsr is composed of one exclusive OR gate and Three triggers, click View RTL schematic under synthesize-XST to view the gate-level circuit generated by the Code, which is consistent with expectation.

Figure 2: RTL schematic

Simulation:

ISE comes with the simulation software isim, but the actual use is not very good. Therefore, we use more professional Modelsim for simulation. For details about how to install and configure Modelsim, see (Baidu. If you have any questions, please leave a message ). After Modelsim is configured, We need to write a testbench to verify the design we just designed. The role of testbench is to add various input excitation signals to the original design, and then observe the output signal waveform. For details about how to write testbench, please write highly efficient testbench on Baidu. The testbench source code of this design is provided here.

 1 `timescale 1 ns / 1 ns 2  3 module lfsr_tb; 4  5 reg                     rst; 6 reg                     usr_clk; 7 wire [2 : 0]            dout    ; 8  9 LFSR  UUT (10         .rst        (rst),11         .usr_clk    (usr_clk),12         .dout       (dout)13         );14 15 always #20     usr_clk = ~usr_clk;16 17 initial begin18         $display("lfsr_tb start...");19         rst = 1;20         usr_clk = 0;21         #100;22         rst = 0;23         #10000;24         $stop;25         end26 27 endmodule

The following is a simple example of Modelsim simulation.

1. Create a New SIM folder and put the source file and testbench file (. H. v) to be used.

2. Open Modelsim and file-New-Project

3. Specify the directory as the created folder and add the. V file to the project.

4. Right-click the. V file in the project and select compile-compile all.

5. Select the library tag, find work, and click + to expand

6. Right-click the compiled. V file and select simulate without optimization.

7. The sim tab is displayed. Right-click the file to be simulated and select Add wave.

8. Set the simulation time, for example, 1000ns

9. Click Run in the toolbar.

Figure 3 shows lfsr simulation results

Figure 3: lfsr simulation waveform

Analysis:

The software used for analysis is mainly chipscope pro. For details about how to use chipscope, refer to "chipscope pro instance tutorial" in Baidu Library search "). The main difference between it and Modelsim is that it is a real board-level debugging. We need to compile the user constraint file (. UCF) based on different development boards. After ise synthesis, the BIT file is generated and written into FPGA after layout and wiring. The main function of chipscope pro is to read FPGA internal signals online in real time through the JTAG port. Here is a problem: Why do we use chipscope to observe the signal? We directly connect the input signal to the LED. Do we know how the signal is changed when we observe that the LED is on or off? Let's use the example we just compiled to briefly explain this problem: the clock signal used in our development board is 33 MHz, and dout will change once on every rising edge of the clock, there will be 33000000 hops in one second, which cannot be distinguished by the naked eye. Therefore, the dout changes cannot be observed through the light-off of the LED. Figure 4 the "dout" change shown by the LED is displayed in the upper left corner.

Figure 4 board-level debugging

For this design task, describe the use of chipscope as much as possible. We decided to use the icon, ILA, and vio cores to analyze the input and output signals at the same time. For detailed operation steps, see blog (http://blog.163.com/bubble_fish/blog/static/237247129201461682452592 ). Figure 5 shows the detected data waveform.

Figure 5 chipscope packet capture