FPGA learning note (4) Modelsim entry and testbench writing -- reasonable use of simulation is king

Start Modelsim step by step and perform simulation through seamless integration with Quartus. This article uses modelsim10.0c + quartuⅱ 10.0. Other versions are basically the same. Please study them on your own.

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1. Set up a third-party EDA tool

In tools-> options, set the installation path of ModelSim. Be sure to set it to the Win32 folder (the 64-bit software corresponds to win64 ).

Create a project (still using the calculator as an example ). In assignments-> Settings, set the simulation tool to ModelSim. In this way, Quartus can seamlessly call ModelSim.

Of course, you can also set up a simulation tool when creating a project.

2. Compile testbench

When it comes to testbench, you can call it testbench or testbenches, but it is not test bench. Even Quartus did not pay attention to this problem. For the reason, see the article common mistakes in technical texts. The article also lists some other incorrect terms, such as flip-flop which cannot be written as flipflop. Article link:

Http://www.sunburst-design.com/papers/Technical_Text_Mistakes.pdf

We can use Quartus to automatically generate a template for testbench and select processing-> Start test execution template writer. After the template is complete, open the generated testbench, saved in the simulation \ Modelsim folder by default. VT format file.

After opening the VT file, you can see that Quartus has completed some basic work for us, including the port code and interface variable declaration, all we need to do is add the required test code in this ready mold.

A basic testbench consists of three parts: Signal definition, Module Interface, and function code.

'Timescale 1ns/1ps indicates that the simulation unit time is 1ns, and the precision is 1 ps. To perform simulation, you must first specify the time unit, and it is best to set the time unit in testbench, instead of defining it in the project code, because different modules may cause some simulation problems if their time units are different, and timescale itself has no impact on the Synthesis, that is, the actual circuit.

In fact, testbench itself can be regarded as a module or device (in this example, the module name is add_vlg_tst) to communicate with your own module. The testbench module outputs signals to the module to be tested as an incentive, and receives signals from the module to be tested to view the results. Therefore, the reg-Type Signal in the module to be tested turns into wire in testbench, And the wire-Type Signal in the module to be tested corresponds to reg-type in testbench. So what about inout? The inout signal should also be set to wire. At the same time, a reg-type signal should be used as the output register, and a three-state gate should be set to be controlled by an enabling signal, for example: assign inout_sig = out_en? Out_reg: 1' BZ;

After processing the interface and declaration, you need to set some incentive signals. The content of the incentive signal is the waveforms that can be input into the module to be tested. Next we will write a simple test program.

First, a reset signal is required:

Initial

Begin

Rst_n = 0;

#100 rst_n = 1;

End

The process starting with initial is executed only once in testbench. #100 indicates that the delay is 100 time units. We have set it through timescale, and the delay is ns. This is a bit similar to the C language. The code is executed sequentially through latency. rst_n is low (that is, the logic is 0) at the time of 0, and NS is then high, forming a power-on reset.

Second, the clock is completed using the always module:

Initial

Begin

Mclk = 0;

End

Always

Begin

#10 mclk = ~ Mclk;

End

The code in the always module will be repeatedly executed. With this feature, the mclk is flipped once every 10 ns, but this still does not work. An initial value is also required for mclk, that is, the above initial statement. In this way, a square wave signal with a period of 20 NS and a frequency of 50 MHz can be generated as the system clock in this example.

Of course, this clock can also be implemented through the initial module. You only need to add a while (1), that is, an endless loop.

Initial

Begin

Mclk = 0;

While (1)

#10 mclk = ~ Mclk;

End

Many operations in testbench are not comprehensive, and their style can be relatively casual.

After setting the clock and resetting, you need to set the input signal:

Initial

Begin

A_in = 1;

B _in = 3;

#200 a_in = 2;

B _in = 0;

#200 a_in = 3;

B _in = 3;

End

Note that a_in = 1 and B _in = 3 occur at the same time, that is, in parallel. The latency is ns, and a_in = 2 at the same time, B _in = 0. As mentioned above, you want to implement sequential operations, latency is required. If there is no latency between the two statements, the statement is executed simultaneously. Another point is that the initial statement block and the initial statement block responsible for resetting are also parallel and start from 0. That is to say, after 0, it is reset by 100ns rst_n, then 100ns (from 0), and a_in = 2 is executed.

Now, the test program has been completed. Let's start simulation.

3. Set Quartus and call the simulation tool

Before running the simulation, set it. On the simulation tab, configure simulation options to configure the simulation language, simulation time format, and output directory. Select mpile test tables and click Test benches to open the test benches dialog box.

Click new to create a test benchsetting, enter the name of the testbench module (here add_vlg_tst), and set the simulation running time (here it is set to 800ns, but the time when the simulation is automatically executed after entering ModelSim,) and add the testbench you just compiled.

After all the steps are OK, choose tools-> RUN EDA simulation tools. There are two options: RTL simulation is an RTL behavior-level simulation. It only verifies whether the function is correct and has nothing to do with the chip on which it runs, the Analysis & synthesis; gate level simulation must be performed at least once before simulation. It involves a specific chip and requires compilation of the project before simulation, in door-level simulation, Modelsim will embody the door-level latency after cabling in the waveform. When testing a specific engineering module, RTL simulation should be performed first, the door-level simulation will be performed later.

4. basic operations of Modelsim

Run RTL simulation to enter the Modelsim interface. Here we will introduce several important parts.

In the View menu, various tool windows can be displayed and hidden. The structure window shows the structure of the test module and the module to be tested:

Click on a different module. In the objects window, you can view the signals in the selected module. In addition to the port, many internal signals do not display waveforms by default, you can display the desired signal by dragging it to the wave window.

The toolbar is used to control the simulation operation. The red box on the left is reset. In the text box, set the execution time and click the button in the red box on the right to execute the operation. For more information, see the Help file.

If you are dizzy with a lot of 0101, you can select the signal in the signal list and right-click the data format to be displayed.

There are several small buttons in the lower left corner of the wave window, which are used to set the cursor. By adding a cursor, you can measure the corresponding time or configure the time scale format here.

In the wave waveform chart, you can use the scroll wheel and right-click to conveniently zoom in or select the waveform area. This is the waveform map of the Full-player project. After resetting, the c_out value is equal to the sum of a_in and B _in, and is output at the rising edge of the clock.

Upload the complete project file (including testbench:

Add.rar