FPGA Learning Path (ix) SPI Protocol communication

SPI Communication Protocol

The SPI is a synchronous serial communication interface.
SPI is the abbreviation of English serial Peripheral interface, as the name implies is the serial peripheral device interface. SPI is a high-speed, full-duplex, synchronous communication bus, the standard SPI also uses only 4 pins, commonly used in MCU and EEPROM, FLASH, real-time clock, digital signal processor and other devices communication. SPI communication principle is simpler than i²c, it is mainly the master-slave communication, this mode is usually only one host and one or more slaves, the standard SPI is 4 lines, respectively, Ssel (chip selection, also writing SCS), SCLK (clock, also writing sck), MOSI ( Host output slave input master Output/slave input) and miso (host input slave outputs master Input/slave output).

Ssel: Select the Enable signal from the device chip. If the device is low-level enabled, when the pin is pulled down, the slave is selected, and the host communicates with the selected slave.
SCLK: The clock signal is generated by the host and is somewhat similar to the SCL of the I²C communication.
MOSI: A channel by which a host sends instructions or data from a slave.
Miso: The host reads the state of the slave or the channel of the data.

In some cases, we can also communicate using the SPI of 3 wires or the SPI of 2 wires. For example, the host only to send commands from the machine, from the machine does not need to reply to the data, that miso can not, and in the host only read from the machine's data, do not need to send instructions from the machine, that Mosi can not; When a host a Slave, The slave can sometimes be fixed to a valid level and has been in the enabling state, then Ssel can not, and if the host only to send data to the slave, then ssel and miso can not, if the host only read the data sent from the machine, Ssel and Mosi can not. 3-wire and 2-wire SPI We need to know what's going on, but the actual use is also applied, but when we refer to the SPI, it is generally referred to as the standard SPI, which refers to the form of 4 lines.

SPI Communication host is our microcontroller, in the process of reading and writing data timing, there are four modes, to understand these four modes, first of all we have to learn about 2 nouns.

Cpol:clock polarity, is the polarity of the clock.
What is the concept of the polarity of the clock? The whole process of communication is divided into idle time and communication time, SCLK the idle state before and after the data is sent is high cpol=1, if the idle state sclk is low, then cpol=0.
Cpha:clock Phase is the phase of the clock.

The host and the confidential exchange of data, it is involved in a problem, that is, when the host output data to the Mosi at what time to sample the data from the machine, or at what time the machine output data to miso and the host at what time to sample the data. one of the characteristics of synchronous communication is that all data changes and samples are accompanied by the clock along the edge, that is, the data will always change or be sampled near the edges of the clock. and a clock cycle must consist of a rising edge and a falling edge, which is determined by the definition of the cycle, except that there is no provision for the succession of the two edges. And since the data from the time of generation to its stability will take a certain amount of time, then, if the host on the rising edge of the output data to the Mosi, the slave can only be on the falling edge to sample the data. Conversely, if one side outputs data on a falling edge, the other party must sample the data on the rising edge.
Cpha=1, it means that the output of the data is on the first edge of a clock cycle , as to whether the edge is rising or falling along, this is the Cpol value, cpol=1 that is the falling edge, and vice versa is the rising edge. then the sampling of the data is naturally on the second edge.
cpha=0, it means that the sampling of the data is on the first edge of a clock cycle, as well as what it is along up to Cpol. then the output of the data is naturally on the second edge.
Think about it, there's a problem here: when a frame of data starts transmitting the first bit, the data is sampled on the first clock edge, so when does it come out? There are two situations: one is the edge of the Ssel enable, the other is the last clock edge of the previous frame of data, and sometimes the two cases will take effect at the same time.

Let's take cpol=1/cpha=1 as an example to show the sequence drawing to everyone, as shown in Figure 1.

As you can see in Figure 15-1, when the data is not sent and when it is sent, the sck are high, so cpol=1. As can be seen, the first edge of the sck, Mosi and miso will change, while the second edge of the SCK, the data is stable, at the moment the sampling data is appropriate, that is, the rising edge is a clock cycle after the latch reading data, that is, cpha=1. Note the last most discreet ssel, typically, this pin is usually used to determine which slave and host are communicating. The remaining three modes, I put the picture out, the simplification of the mosi and miso together, we look closely at the study, all the theoretical process is clear, conducive to your deep understanding of SPI communication, as shown in Figure 2.

Verilog Programming

The communication protocol used in the program design is shown above in Figure 1, i.e. (cpol=1/cpha=1) programming Steps:

Receiving module:
1) Synchronization of data between MCU side and FPGA end.
SPI data from the MCU output, MCU and FPGA is not the same clock domain, you can use the simplest D trigger to achieve data synchronization. The edge detection of the rising edge requires two D flip-flops, in order to ensure the synchronization of the SPI data, the other signals are also synchronized through two levels of trigger output.
Access Spi_data signal and edge detection spi_cs and SPI _sck signal:spi_sck rising edge output data flag; Spi_cs rising edge for write data completion flag.
2) design of SPI Communication Protocol (data reception).
Determine if the Spi_cs is valid, capturing 8 bits of data based on the receive enable signal (the MCU timing is rising along the sampled signal), and the capture of the data is implemented by a counter count.
3) Capture the output of the enabled signal after completion.
Convenient back-end response, output capture complete signal flag.

Send module:
1) Synchronization of data between MCU side and FPGA end.
Only edge detection spi_cs and SPI _sck signals are required:the Spi_sck drop Edge is written to the data flag, and the Spi_cs rising edge is the write data completion flag.
2) design of SPI Communication Protocol (data reception).
The state machine is used to design the sending protocol, two States are designed, State 1 is the idle wait state data output is always 0, state 2 is the send state, output and the data is transferred sequentially.
3) The output of the enable signal after the data is sent.
Convenient back-end response, output signal sign. The signal is determined by the CS rising edge.

This part of the theory is quoted from:
Http://www.diangon.com/wenku/rd/danpianji/201501/00017903.html