FPGA optimization discussion: Solution to the clock gate and multiple fan-out problems

FPGADuring the design, the wiring problem caused by unreasonable design often occurs. One of the more prominent problems is the door clock and multi-fan-out problems.

 

The clock is not used.FPGAInternal global clock ResourcesBufgTo control the trigger clock along the input end, the signal generated by the combination logic and other time series logic (such as the divider) is used as the trigger clock along the input end. The Clock is easy to cause clock drift and glitch, making the trigger operate by mistake. Generally, the compiler can automatically optimize the wiring of the distributed clock buffer for a few triggers, however, the clock with many driver triggers will cause unstable wiring and serious problems in design confusion. A large number of gators can reduce the maximum operating speed of the entire design and reduce the product performance.

 

The common solution to the clock gate problem is to generate a pulse signal with a cycle width equal to the system clock width. The so-called system clock is to use global clock resources.BufgA high fan-out, zero-drift, and zero-distortion clock ResourceFPGAThe internal wiring structure is a tree structure.

 

Sends the output of the divider to the triggerCEDetection when the system clock arrivesCESignal validity whenCEWhen the signal is valid, the trigger output is changed, which is exactly the same as that of the divider, and this processing also makes the wiring more optimized.

 

For multi-fan-out problems, it usually refers to the use of one node to drive multiple lower-level logical devices. For triggers with a large number of clock-controlled drivers, it can also be classified as such problems, this problem will seriously affect the stability of FPGA cabling. pay more attention to this issue during design. At this time, the replication register policy is used:

 

The CLK is the system clock, and the M1 is a 1 MHz square wave signal. Because there are many modules driven by the M1 signal, the M1 fan out is much larger (assuming that the fan out number is 140). To reduce fan out, sample with the system clock, Drive 7 d triggers by M1 signal, and then distribute the output of 7 d triggers to 7 modules, so that each replication point (dup0 ~ Dup6) the average fan output is 20, and the M1 signal fan output is 7. This reduces the fan output of each signal, optimizes the logic, and improves the overall performance of the design.

 

The following is a description of the above-mentioned module in VHDL:

 

Library IEEE;

Use IEEE. std_logic_00004.all;

 

Entity regdup is

Port (CLK: In std_logic;

       DUP: Out std_logic_vector (6 downto 0 );

       M1: In std_logic );

End regdup;

 

Architecture RTL of regdup is

Begin

Process (CLK)

Begin

 If CLK 'event and CLK = '1' then         -- System clock sampling

   DUP (0) <= m1;           -- Copy M1 Signal

   DUP (1) <= m1;

   DUP (2) <= m1;

   DUP (3) <= m1;

   DUP (4) <= m1;

   DUP (5) <= m1;

   DUP (6) <= m1;

 End if;

End Process;

End RTL;