FPGA programming Tips and experience notes

1, bit splicing operation must specify the number of digits , if not indicated by the implied 32-bit binary number "that is an integer". Example: {1,0} = "h00000001_00000000"; Not equal to 2 ' B10;

2,% modulo operation or take-up operation can be implemented with "and" operations to achieve a fast residual operation.

For example , a%4 can be reduced to a&3. Detailed: 5%4 = 4 ' b0101%4 ' b0100//Because the remainder is smaller than 4, so the remainder of the bit2 bit and above bits are 0, only bit0, bit1 have data, and the original number is the same

= 4 ' b0101&4 ' b0011 = 4 ' b0001 = 1;

So as long as the number of modulo is 2^n number can do so. The advantage is that bit operations require only a single instruction cycle, while the majority of the C compiler's "%" operations are done by calling subroutines, with long code and slow execution times.

3,% operation is different from ordinary operation, more strict. Requirements: The two sides of the shape of thedata, and the result of the value of the symbol and take the remainder of the first number of symbols in the operation.

If the operand is negative, the remainder is positive, that is, B%a,b<0,a>0,a, b are all integers,

Then what will the result be? The simulation results with Modelsim are as follows:

You can see that the symbol of quotient and remainder is the same as the symbol of the number of remainders.

4. The operation symbol of power is * *, while the operation symbol of ^ refers to bitwise XOR or Attribution .

^ Bitwise XOR: Two Yuan Xor, there are two operands located on both sides. If a bit is x or Z, the bit result is x, otherwise the same is 0, and the difference is 1.

4 ' b0110^4 ' b1000 = 4 ' b1110;

^ Attribution or: unary operand, if the value of a bit is x or Z, the result is x, if there is an even number of 1 in the operand, the result is 0, otherwise 1;

^4 ' b0011 = 0;

^4 ' b0001 = 1;

FPGA programming Tips and experience notes