FPGA static timing analysis model-register-to-register

Document directory

• 3.1.1 fixed parameter launch edge, latch edge, Tsu, th, and TCO concepts
• 3.1.2 clock skew
• 3.1.3 data arrival time
• 3.1.4 clock arrival time
• 3.1.5 data required time (Setup/hold)
• 3.1.6 setup slack
• 3.1.7 minimum clock cycle
• 4.1.1 single-clock Constraints
• 4.4.1 Synplify timing report
• 4.4.2 designer smarttime Sequence Analysis Report
• 4.4.3 detailed Time Series Report Diagram

1. Applicability

This document applies to actel FPGA and uses Libero software for static timing analysis (register to register ).

2. Application background

Static timing analysis is short for Stas. It is an exhaustive analysis method. According to the requirements of the synchronous circuit design, according to the topological structure of the circuit network table, calculate and check whether the establishment and retention time of each DFF (trigger) in the circuit and other path-based latency requirements are met. As one of the main verification methods for FPGA design, Sta does not require the designer to write test vectors. The software automatically completes the analysis. The verification time is greatly shortened, and the test coverage rate can reach 100%.

The premise of static time series analysis is that the designer first puts forward the requirements, and then the time series analysis tool will analyze according to the specific time series model and give the correct time series report.

The main purpose of static timing analysis is to increase the clock speed and stability of the system. For many digital circuit designs, it is very important to increase the operating frequency, because high operating frequency means high processing capability. Additional constraints can be used to control the synthesis, ing, layout, and wiring of logic to reduce the delay of logic and wiring and increase the working frequency.

3. Theoretical Analysis 3.1 basic theoretical knowledge of static Time Series Analysis

Before performing a correct timing analysis, we must have basic knowledge about the static timing. Otherwise, we will look at the timing analysis report provided by the compiler as if it were tianshu. 3.1 shows the capture of the timing analysis report from the Register to register model provided by the libero software. Next we will figure out the meaning of the data variables in each column and the calculation method.

Figure 3.1 Libero static timing analysis report

3.1.1 fixed parameter launch edge, latch edge, Tsu, Th, TCO concept 1. Launch edge

 

Launch edge: the clock edge of the first-level register data change, which is also the starting point of static time series analysis.

2. Latch edge

Latch edge: the end point of the static time series analysis.

3. Clock setup time (TSU)

Creation Time (TSU): the time required for data to be unstable before the clock arrives, if the created time does not meet the requirements, the data cannot be steadily pushed into the trigger on the rising edge of the clock. 3.2:

 

Figure 3.2 creation time diagram

4. Clock hold time (th)

Retention time (th): it is the time after the index data is stabilized. If the retention time does not meet the requirements, the data cannot be stably written into the trigger. The retention time is 3.3:

 

 

Figure 3.3 persistence time diagram

5. Clock-to-output delay (TCO)

Data Output latency (TCO): this refers to the minimum time interval between the input and output ends of data when the clock is effective along a change.

3.1.2 clock skew

Clock skew (clock skew): refers to the time offset when a clock source reaches the clock ends of two different registers, as shown in Figure 3.4:

 

 

Figure 3.4 clock skew

The formula for calculating the clock skew is as follows:

Tskew = tclk2-tclk1 (Formula 3-1)

3.1.3 data arrival time

Data arrival time: the time required for the input data to arrive after the valid clock edge. The clock arrival Register time (tclk1), register output latency (TCO), and data transmission latency (tdata), as shown in Figure 3.5

 

Figure 3.5 data arrival time

The formula for calculating the data arrival time is as follows:

Data arrival time = launch edge + tclk1 + TCO + tdata (Formula 3-2)

3.1.4 clock arrival time

Clock arrival time (clock arrival time): the time consumed by the clock to arrive at the clock input end of the lock register from the latch edge is the clock arrival time, as shown in Figure 3.6.

Figure 3.6 clock arrival time

The formula for calculating the clock arrival time is as follows:

Clock arrival time = lacth edge + tclk2 (Formula 3-3)

3.1.5 data required time (Setup/hold)

Data required time: data must be stable between the creation time and the retention time of the clock lock. The time required to reach the stable state from the source clock start point is the data requirement time. 3.7:

 

 

Figure 3.7 data requirement time

(Established) the data demand time calculation formula is as follows:

Data required time = clock arrival time-Tsu (Formula 3-4)

The formula for calculating the data requirement time is as follows:

Data required time = clock arrival time + Th (Formula 3-5)

3.1.6 setup slack

Setup slack: when the data demand time exceeds the data arrival time, there is a margin for the time. Slack is a title that indicates whether the design meets the time sequence.

Figure 3.8 create a time margin

3.8. The formula for creating a time margin is as follows:

Setup slack = data required time-data arrival time (Formula 3-6)

According to the formula, a positive slack indicates that the data demand time is greater than the data arrival time to meet the time sequence (timing margin), and a negative slack indicates that the data demand time is less than the data arrival time, does not meet the time series (the amount of time series lacking ).

3.1.7 minimum clock cycle

Minimum clock cycle: the maximum frequency at which the system clock can run.

1. When the data demand time exceeds the data arrival time, the clock has a margin;

2. When the data demand time is less than the data arrival time, the time sequence requirement is not met, and the register goes through the sub-steady state or cannot obtain the data correctly;

3. When the data demand time is equal to the data arrival time, this is the minimum clock operation frequency, just to meet the time series.

From the preceding three points, we can conclude that the minimum clock cycle is that the data arrival time is equal to the data demand time. The calculation formula is as follows:

Data required time = data arrival time (Formula 3-7)

The formula above is as follows:

Tmin + latch edge + tclk2-Tsu = launch edge + tclk1 + TCO + tdata

The minimum clock cycle is:

Tmin = TCO + tdata + Tsu-tskew (Formula 3-8)

4. Application Analysis 4.1 set clock speed Constraints

All static timing analysis reports are provided by the compiler only when there are constraints. Therefore, the first step for timing analysis is to set constraints.

The Libero software sets three clock constraints: one clock constraint, multiple clock constraints, and constraints in the designer.

4.1.1 single-clock Constraints

Sometimes all modules in our system adopt the same clock. This method is the easiest. There is a clock constraint on the Synplify main interface, as shown in the red box in 4.1:

 

 

Figure 4.1 single-clock setting

After the settings are complete, compile and use the Synplify clock report to check whether the initial clock running frequency can meet the requirements. The clock report is 4.2, which is set to 100 MHz and can run 102.7 MHz to meet the time sequence.

 

 

Figure 4.2 Time Series Report

More than 4.2 clock Constraints

When multiple clocks are used in the internal modules of the system, multiple clock constraints are required. First, you need to open the settings page and select File> New> constraint file in Synplify to create an SDC file. Select clock constraint 4.3:

 

 

Figure 4.3 multiple clock Constraints

Save the SDC file after the following constraints are imposed on the clock, as shown in constraint 4.4

Figure 4.4 completion of multiple clock Constraints

4.3 designer smarttime clock Constraints

In addition to being constrained in Synplify, you can also set clock constraints in designer smarttime, enable designer constraint, and select clock to set each clock, as shown in Figure 4.5:

Figure 4.5 timing constraints of designer

4.4 timing report analysis 4.4.1 Synplify timing report

When the time series is constrained, You need to observe the Time Series Report to see if the clock can reach the clock we need. First, observe the Synplify comprehensive report. Taking multiple clock constraints as an example, the timing report 4.6 obtained from Synplify is shown below:

 

Figure 4.6 Time Series Report with multiple clock Constraints

We can see that the time series meet the constraints and there is no violation. You can view the worst path in the following report. 4.7 shows the worst path of clk2.

Figure 4.7 worst path

4.4.2 designer smarttime Sequence Analysis Report

After Synplify provides the network Table file, you also need the designer to perform layout and wiring, and the timing after layout and wiring optimization will change. Therefore, you also need to analyze the time sequence after layout and wiring, open designer-> Timing Analyzer to view the overall timing analysis report 4.8:

Figure 4.8 timing report after layout and wiring

The report after Synplify and the report after designer layout and wiring can be seen that some time series are optimized after layout and wiring, especially the clk2 clock, which is optimized to 184 MHz after layout and wiring, the time sequence is fully satisfied.

4.4.3 detailed Time Series Report Diagram

After Synplify and designer are integrated, layout and wiring only shows a general Time Series Report. When we need to analyze the time series, we must observe the careful Time Series Report, this report function is provided in smarttime. Take clk2 as an example to find the following area in Timing Analyzer.

 

Figure 4.9 timing report Selection

As shown in figure 4.9, select the Register to analyze the clock speed.

 

 

Figure 4.10 register-to-register Analysis

As shown in 4.10, the time series report provides information such as data delay, time series margin, data arrival time, data demand time, data creation time, minimum cycle, and clock skew, with the basic knowledge of time series analysis in the previous section, we can fully understand the meaning of the data. In this way, we can know ourselves and ourselves in time series analysis and double-click a path, the hardware circuit diagram of this path is also provided, as shown in Figure 4.11. With these detailed time series Reports, the design adjustment is clearer.

Figure 4.11 hardware path