From cortex-m3 to cortex-M4 (4) -- Cortex-M3, 4 Comparison

1. Memory Protection Unit MPU

Similar to Cortex-M3, MPU is an optional component used for memory protection in Cortex-M4. The processor supports the standard ARMv7 memory protection system structure model. You can run privileged/access rules or independent processes on the MPU. This MPU provides comprehensive support:

· Protected Area

· Overlapping protection areas to improve the priority of the Region (7 = highest priority, 0 = lowest priority)

· Access Permissions

· Output storage attributes to the System

2. DSP capability

The chart shows the relative performance of Cortex-M3 and Cortex-M4 in digital signal processing capabilities when the processor runs at the same speed.

In the following number, the Y axis represents the relative number of cycles used for execution. Therefore, the smaller the number of loops, the better the performance. With Cortex-M3 as a reference, the performance ratio of Cortex-M4 is approximately the reciprocal of its cyclic count. Example: PID function, Cortex
-The period number of M4 is about 0.7 times that of Cortex-M3, so the relative performance is 1/0. 7, that is, 1.4 times.

 Cortex-M Series 16-bit cyclic count function

 

Cortex
-32-bit cyclic count function of the M series

 

This clearly indicates that Cortex
-M4 has a great advantage over Cortex-M3's 16-bit or 32-bit operations in digital signal processing.

All DSP instruction sets executed by the Cortex-M4 can be completed in one cycle, and Cortex-M3 requires multiple instructions and multiple cycles for equivalent functionality. Even if the PID algorithm is the most resource-consuming job in general DSP operations, Cortex-M4 provides a performance improvement of 1.4 times. In another example, MP3 decoding requires 20-25 Mhz in the Cortex-M3, while only 10-12 MHz in the Cortex-M4.

1. 32-bit multiplication and accumulation (MAC)

32-bit multiplication (MAC) includes a new instruction set and optimization for the Cortex-M4 hardware Execution Unit. It is able to complete a 32
* 32 + 64-> 64 operations or two 16*16 operations. The following table lists the computing power of this unit.

 

2. SIMD

Cortex-M4 supports the SIMD instruction set, which is unavailable in the previous generation of Cortex-M series. Some commands in the preceding table are SIMD commands. Work with hardware multiplier (MAC) so that all these commands can be executed within a single cycle. Benefiting from the support of SIMD commands, the Cortex-M4 processor is able to complete up to 32x32 + 64-> 64 operations in a single cycle, releasing the bandwidth of the processor for other tasks, instead of consuming computing resources by multiplication and addition. Consider the following complex arithmetic operations, where two 16 × 16 multiplications plus A 32-bit addition are compiled into A single command for execution: SUM = SUM + (A * C) + (B
* D)

3. FPU

FPU is an optional unit for Cortex-M4 floating point operations. Therefore, it is a unit dedicated to floating point tasks. This unit improves performance through hardware, can handle Single-precision floating point operations, and is compatible with the IEEE 754 standard. This completes the floating point expansion of single precision variables in the ARMv7-M architecture. FPU extends the register program model and register files that contain 32 single-precision registers. These can be seen:

· 16 64-bit dual-character registers, D0-D15

· 32 32-Bit Single-word registers, S0-S31 this FPU provides three modes for various applications

· Full compatibility mode (in full compatibility mode, FPU handles all operations in compliance with IEEE754 hardware standards)

· Flush-to-zero fl to zero mode (set the FZ-bit floating point status and control register fpscr [24] To flush-to-zero mode. In this mode, FPU treats all the arithmetic CDP operations of Abnormal Input operands as 0, except when the result of the first operand is appropriate. Vabs, vneg, and vmov are not considered as arithmetic CDP operations and are not affected by the flush-to-zero mode. The result is tiny. As described in the IEEE 754 standard, the increase in the target precision is less than the minimum normal value after rounding, and is replaced by zero. The identifier of the IDC, fpscr [7], indicates that the field changes when the input is flush. UFC flag, fpscr
[3], indicating changes when flush ends)

· The default Nan mode (for the DN bit setting, fpscr [25] will enter the default mode of Nan. In this mode, if the result of any arithmetic data processing operation involves an input Nan or produces an Nan result, the default Nan is returned. Only when vabs, vneg, and vmov operations are performed, the fractional bit is increased and maintained. All other CDP operations will ignore information about the decimal places of all input Nan)

The following table shows the FPU instruction set.

3. Debug

Similar to cortex-m3, cortex-M4 devices debug connectors through standard jtags or serial lines. To connect to the host interface, a simple, standardized external connector is necessary.

4. Power supply

1. Power Management

 

 

 2.Power Consumption comparisonAs shown in the figure, the performance of cortex-M4 is significantly better than that of table cortex-m3 in terms of power efficiency.