Full-Add Device

The/*4-bit full adder requires input and output, and requires a subordinate up-up input, which requires an upward-carrying output. Let's see, this module already contains all the input and output information. As we all know, the N-bit adder comes out and is at most n+1 bits so you can clearly see the relevant information from the code below. The assign is then used for blocking assignments. Add up to meet the relevant requirements. */module adder4 (cout,sum,ina,inb,cin);    OUTPUT[3:0] sum;    Output cout;    INPUT[3:0] INA,INB;    Input cin;        Assign {Cout,sum}=ina+inb+cin;endmodule

Before writing Testbeach files, popularize a little bit of Testbeach knowledge:
Generally speaking, when the data type is declared, the signal connected to the input port of the tested module is defined as the Reg type, which makes it easy to assign the value in the initial statement and the always statement block, and the signal connected to the output port of the measured module is defined as the wire type for easy detection. The most important task of the Testbench module is to use a variety of legitimate statements, generate appropriate timing and data to complete the test, and achieve coverage requirements.

Then the Testbeach file is as follows:

/*file Name:test_adder4.vDescription:The Testbench of the Adder_4.vwritten by:limingdata : 2011/04/18 20:13modefied: When simulating, change the delay from 10ns to 5ns:cout display as 2-bit *///test_adder4 (top-level module) ' Ti        Mescale 1ns/1nsmodule test_adder4;    Declare variables wire[3:0] sum;    Wire cout;    REG[3:0] INA,INB;        Reg CIN;        Instantiate the module adder4 adder4 adder4_1 (cout,sum,ina,inb,cin); Stimulate the inputs, Finish the stimulation at time units initial begin #0 ina = 4 ' b0001; INB = 4 ' b1010;            cin = 1 ' b0; #5 ina = 4 ' b0010; INB = 4 ' b1010;            cin = 1 ' B1; #5 ina = 4 ' b0010; INB = 4 ' b1110;            cin = 1 ' b0; #5 ina = 4 ' b0011; INB = 4 ' b1100;            cin = 1 ' B1; #5 ina = 4 ' b0111; INB = 4 ' b1001;            cin = 1 ' b0; #5 ina = 4 ' b0001; INB = 4 ' b1100;            cin = 1 ' B1; #5 ina = 4 ' b0011; INB = 4 ' b1100;            cin = 1 ' b0; #5 ina = 4 ' b0111; INB = 4 ' b1111;      cin = 1 ' B1;      #5 $finish; End initial $monitor ("At Time%t, Ina (%b) + INB (%b) + cin (%b) = SUM (%b) (%2d), cout (%b)", $time, Ina, INB, CIN    , Sum, sum, cout);            Initial begin $dumpfile ("TEST.VCD");        $dumpvars (0,TEST_ADDER4); Endendmodule

Full-Add Device