Gd32 chip transplantation

Gd32 is a fully compatible Cortex-M3 processor of stm32 series, which is made by Zhao Yi INNOVATION company. It has several highlights:
1,High clock speed 108 MHz. Performance is improved by more than 30%, and super-frequency to 120 MHz is supported
2,Flash Zero Wait. The MHz of stm32 requires two waits. In fact, zhaoyi INNOVATION company started out as flash and owns gflash patents.
3,Using arm Cortex-M3 new kernel r2p1. Stm32 adopts r1p1 with some defects
4,Cost-effective. Gd32 is generally 20% cheaper than the corresponding stm32 chip, and some chips are more than 30% cheaper

After receiving the sample gd32f103vet6, replace stm32f103vet6, write the latest tinybooter and MF firmware versions, and the MF test routine, all of which pass at once!
Excellent compatibility.
However, we cannot meet this requirement. The MF firmware runs at the 72mhz clock speed by default, and Flash still uses two waits. We need to test a higher speed!
Therefore, according to official information, the clock speed was changed to 108 MHz, and Flash was set to zero wait.

RCC-> cfgr | = (uint32_t) (0x08000000 | rcc_cfgr_pllsrc_hse | rcc_cfgr_pllxtpre_hse_div2 | rcc_cfgr_pllmull12 );

After modification, the USB cannot be identified and the serial port is messy!
The above is the most data available on the Internet, which means HSE/2 * (12 + 15). divided by 2 and 12, we can understand it. If it comes out of 15, we really don't understand it.

Request the official technical support and receive an email response in a few minutes.
The general idea is that the listen MHz cannot obtain the 48 MHz required by the USB. The stm32 originally supports the 1-and 1.5-based distribution, and then the gd32 expands the 2-and 2.5-based distribution. Therefore, if you want to use USB, either reduce the frequency to 96 MHz or overclock to 120 MHz, then you can obtain the 48 MHz required by USB by dividing the frequency by 2 or 2.5 separately.
This means that gd32 cannot use USB under standard megamhz, so please have a cup !!!

In addition, for serial port garbled characters, the reply to me is to modify the rcc_getclocksfreq function:

void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks){  uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;  /* Get SYSCLK source -------------------------------------------------------*/  tmp = RCC->CFGR & CFGR_SWS_Mask;   switch (tmp)  {    case 0x00:  /* HSI used as system clock */      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;      break;    case 0x04:  /* HSE used as system clock */      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;      break;    case 0x08:  /* PLL used as system clock */      /* Get PLL clock source and multiplication factor ----------------------*/      pllmull = RCC->CFGR &((uint32_t)0x203C0000);      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;          if(((pllmull)&(0x20000000)) != 0)          pllmull = (((pllmull)&(0x003C0000)) >> 18) + 17;      else          pllmull = ( pllmull >> 18) +2;            if (pllsource == 0x00)      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;      }      else      {        /* HSE selected as PLL clock entry */        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)        {/* HSE oscillator clock divided by 2 */          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;        }        else        {          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;        }      }      break;    default:      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;      break;  }  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/  /* Get HCLK prescaler */  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;  tmp = tmp >> 4;  presc = APBAHBPrescTable[tmp];  /* HCLK clock frequency */  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;  /* Get PCLK1 prescaler */  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;  tmp = tmp >> 8;  presc = APBAHBPrescTable[tmp];  /* PCLK1 clock frequency */  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;  /* Get PCLK2 prescaler */  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;  tmp = tmp >> 11;  presc = APBAHBPrescTable[tmp];  /* PCLK2 clock frequency */  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;  /* Get ADCCLK prescaler */  tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; tmp = (tmp >> 14)+(tmp >> 26);  presc = ADCPrescTable[tmp];  /* ADCCLK clock frequency */  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;}

The approximate meaning is to judge a flag. If there is a flag, another formula is used to calculate the multiplier. For the moment, I guess that the flag is dedicated to gd32.
However, this will not solve my problem. Our MF system uses registers to set the baud rate, and there is no library function at all. I just want to clarify why I want to modify it like this, and then I operate the register like Huludao. As a result, I failed. Here, 17 is as inexplicable as the 15 above, but + 17 is much better than the previous + 2 below. What does it look like.

Use 0x20000000 as the switch entry to view its usage in RCC-> cfgr.

It is actually dedicated to gd32, and 0x20000000 is a 29th-bit Reserved Bit.
Xiaofei thinks this digit is related to the previous 15, so we try to change the 0x08000000 used in the previous division to 0x20000000.

RCC-> cfgr | = (uint32_t) (0x20000000 | rcc_cfgr_pllsrc_hse | rcc_cfgr_pllxtpre_hse_div2 | rcc_cfgr_pllmull12 );

At this time, the system ran up and the serial port was not garbled, but the USB port was not usable. Of course, USB was not available at 108mhz.
This solves the problem of serial port garbled characters.
However, there is a very strange problem. We can see that the system clock is 48 MHz during Keil debugging, and the conversion through registers is also a bit confusing!
Hua Ge reminded that the RCC debugging interface of Keil is prepared for stm32, and the special frequency of gd32 may be inaccurate.
In fact, the key lies in the 29 BITs. Due to its existence, the rcc_getclocksfreq function ignores 29 BITs when calculating the 108mhz Division, resulting in 48 MHz, that is, 8 m/2*12, the 15th is missing.
Therefore,Gd32 beginners need to modifyRcc_getclocksfreq is used to set the frequency calculation result to 108 MHz to solve serial port garbled characters.. WhileWhen I use 0x0800000, the MCU actually works at 48 MHz, and when I calculate the baud rate on the serial port, I use 108 MHz.. The two made different mistakes, resulting in the same results, and then solved the problem.
Many people have asked me to wait for a proportional conversion frequency. m is 1.5 times the ratio of m to 72 m, and then calculate the baud rate. But I am not convinced, because f407 is 168 m, which is also the formula.
Conclusion:The key to serial port garbled characters is that the baud rate calculation frequency must be consistent with the actual MCU frequency.!

For the MF system, USB cannot be used, so we test 96 MHz and 120 MHz, respectively 12-frequency and 15-frequency, USB 2-frequency and 2.5-frequency, which is very easy to calculate!
It is found through Keil debugging that the system is successfully operating at 96 MHz and 120 MHz, but the displayed USB frequency is sometimes 64 MHz, Sometimes 96 MHz/80 MHz/120 MHz, which is very puzzling!
PC cannot find USB device, very depressed!
Later, I accidentally cleared the flash chip and realized that tinybooter was started at MHz, but tinyclr was still running at 72 MHz, so I could not find the USB.
After re-compiling tinyclr to MHz, the problem was solved and USB was found.
In addition, when tinyclr is refreshed, the speed is significantly faster, about 100 kb/s.

In fact, these problems may not be very difficult, but there is no uniform and detailed documentation on the official side (I have not made it clear why it was changed ).
I found a message on the Internet afterwards:

Q: What is the difference between gd32f105/107 MCU series configured with 108mhz? A: In clock configuration register (rcc_cfgr), The 21:18 bits are pllmul [], and a 5-bit domain consisting of 29th bpllmul [4] is used to determine the PLL multiplier, That is, the frequency doubling factor of the PLL is defined through software configuration, and the output frequency of the PLL must not exceed the maximum frequency (108 MHz ).

It's really a pitfall. Do you have wood ???

50% MHz clock speed, with Flash Zero Wait, the performance improvement should be more than. For MF with insufficient performance, it is very good!
As to whether it is stable or not, I don't understand it. Just install the pipeline and try it!

End.

Turn stone brother

Gd32 chip transplantation