Generate FIFO using quartuⅱ

Quartus ii lpm User Guide

FIFO

Directory

Description-2-

Summary-3-

Chapter 1 Introduction to FIFO configuration-4-

1.1 how to configure the required FIFO-4-

1.2 input/output port-5-

1.3 Timing requirements-8-

1.4 output status tag and latency-8-

1.5 avoid sub-steady state-9-

1.6 impact of Synchronous Reset and Asynchronous Reset-9-

1.7 different input/output bits-10-

1.8 constraint settings-10-

Chapter 2 Design Example-11-

2.1 design instance overview-11-

2.2 System Simulation Analysis-11-

2.2.1 write operations-11-

2.2.2 Read operation-12-

2.2.3 when dcfifo is full-13-

2.2.4 complete data transfer from Rom to dcfifo-13-

2.2.5 complete data transfer from dcfifo to ram-14-

Appendix FIFO configuration page:-15-

1-15-

2-16-

3-17-

4-18-

5-19-

6-19-

References-21-

Description

This document is based on the question "scfifo and dcfifo megafunctions" of Altera.

The author uses the Quartus II version and the pc OS version as 11.1 SP2 win7 32-bit.

This document is for study and discussion purposes only. Do not use it for commercial purposes. If you have any questions when using this document, please go to the author's blog for discussion.

Document version V1.0

I will change the content of this tutorial at any time without prior notice.

Summary

Altera provides configurable single-clock FIFO (scfifo) and dual-clock FIFO (dcfifo) in the LPM library ). FIFO is mainly used in synchronous or asynchronous scenarios where data buffering is required and the data conforms to the FIFO rule. The FIFO in LPM contains the following types:

1. scfifo: Single-clock FIFO;

2. dcfifo: Dual-clock FIFO, with the same data input and output width;

3. dcfifo_mixed_widths: Dual-clock FIFO. The input/output data bit width can be different.

In this article, unless otherwise stated, dcfifo refers to the two dual-clock FIFO.

Chapter 1 Introduction to FIFO configuration 1.1 how to configure the required FIFO

You can use either of the following methods to configure FIFO: select the FIFO parameter editor in megawizard plug-in manager under tools in Quartus II to set up the required FIFO, this is an automatic FIFO method, and if you are a master (very familiar with LPM-FIFO parameters) You can also manually write the HDL to achieve the required FIFO. I suggest that you, especially for beginners, use the automatic method to configure the required FIFO. The configuration interface is simple and easy to use.

1.2 input and output ports

The block diagram of scfifo and dcfifo is displayed. The signal of both read and write sides of scfifo is synchronized with the clock, and the signal of both sides of dcfifo read and write is synchronized with the Read and Write clock respectively.

Table 1 lists the detailed descriptions of each IO in the FIFO:

Table 1 port description

Port

Type

Required

Description

Clock

Input

Yes

Rising edge trigger clock

Wrclk

Input

Yes

The rising edge triggers the clock, and the following signals are synchronized with it:

Data

Wrreq

Wrfull

Wrempty

Wrusedw

Rdclk

Input

Yes

The rising edge triggers the clock, and the following signals are synchronized with it:

Q

Rdreq

Rdfull

Rdempty

Rdusedw

Data

Input

Yes

When wrreq is valid, data on the data line is written to the FIFO through the data port.

Wrreq

Input

Yes

Write Request signals to stimulate write operations.

1. When full (for scfifo) or wrfull (for dcfifo) is valid, the wrreq signal cannot be activated, and the overflow_checking parameter is set to on, that is, the FIFO will automatically ignore write requests in full State;

2. The wrreq signal cannot be activated when ACLR is valid;

3. Use the Stratix and cyclone series devices (except for the Stratix, Stratix GX, and cyclone series) to select the write_aclr_synch parameter bit on to ensure that the constraints are met.

Rdreq

Input

Yes

Read Request signals to stimulate read operations.

1. The functions of this signal are different in normal mode and in pre-Read mode (For details, refer to the following article );

2. When empty (for scfifo) or rdempty (for dcfifo) is effective, the rdreq signal cannot be activated, and the underflow_checking parameter is set to on, that is, the FIFO will automatically ignore read requests in full State;

SCLR

ACLR

Input

Non

Clear the port. For more information, see the following section.

Q

Output

Yes

Output the data read from the FIFO by the read operation.

1. In scfifo and dcfifo, the input and output data must have the same bit width;

2. dcfifo_mixed_widths type FIFO input/output bits can be different, but the input/output bits/width ratio varies depending on the ram type;

Full

Wrfull

Rdfull

Output

Non

When the signal is valid, the first-in-first-out (FIFO) is considered to be full and cannot be written;

Empty

Wrempty

Rdempty

Output

Non

When this signal is valid, the first-in-first-out (FIFO) is considered to be empty and cannot be read;

Almost_full

Output

Non

Quasi-fill signal. When usedw is greater than almost_full_value or is the same, the signal is activated, indicating that the full signal is activated;

Almost_empty

Output

No

Quasi-read empty signal. When usedw is smaller than almost_empty_value or is the same, the signal is activated, indicating that the empty signal is activated;

Usedw

Wrusedw

Rdusedw

Output

No

Displays the data inventory in the current FIFO.

Table 2 lists the parameters for configuring FIFO:

Table 2 parameter description

Parameters

Type

Required

Description

Lpm_width

Integer

Yes

For scfifo and dcfifo, this parameter defines the Bit Width of data and Q, and for dcfifo_mixed_widths, this parameter defines the width of data;

Lpm_width_r

Integer

Yes

For dcfifo_mixed_widths, this parameter defines the width of Q;

Lpm_widthu

Integer

Yes

For scfifo, this parameter defines the usedw port bit width. For dcfifo, it defines the Bit Width of rdusedw and wrusedw, and for dcfifo_mixed_widths, it defines the Bit Width of the wrusedw port;

Lpm_widthu_r

Integer

Yes

For dcfifo_mixed_widths, the bit width of the rdusedw port is defined;

Lpm_numwords

Integer

Yes

The FIFO depth is defined with a value of at least 4 and needs to meet the following relationship 2 ^ (LPM_WIDTHU-1) <lpm_numwords £.

<2 ^ (lpm_widthu)

.

Lpm_showhead

Yes

Select normal or pre-Read mode.

In normal mode, data is read only when rdreq is valid;

In pre-Read mode, the first data in the current FIFO is automatically read (when the FIFO is not empty). When the rdreq signal is valid, the system starts to read the second data in the future;

Lpm_type

Non

Identify parameters of the FIFO model, scfifo or dcfifo

Maximize_speed

Integer

Non

Space or Speed Optimization Parameter. The value is 0-5 and the value is 6-10.

Overflow_checking

Non

Whether to enable overflow detection. wrreq is ignored during overflow. The value is no or off. The default value is on;

Underflow_checking

Non

Whether to enable underflow detection. When underflow (read empty) is enabled, rdreq is ignored. The value is no or off and the default value is on;

Delay_rdusedw

Delay_wrusedw

Non

Add_usedw_msb_bit

Non

This parameter is used to increase the Bit Width (1 bit) of rdusedw and wrusedw to prevent the first packet from being flipped to 0 when the first packet is full. The parameter value is on or off and the default value is off. This parameter is only valid for certain series devices.

Rdsync_delaypipe

Wrsync_delaypipe

Integer

Non

Use_eab

Non

Whether to use block ram to construct FIFO. The value of this parameter is on or off. If it is set to off, use le to construct FIFO;

Write_aclr_synch

Non

Whether to set ACLR to be synchronized with wrclk to avoid competition between wrreq and ACLR. The default value is off, which is only valid when some devices are used;

Clocks_are_synchronized

Non

Ram_block_type

Non

Add_ram_output_register

Non

Select whether to store Q output data;

Almost_full_value

Integer

Non

Set the threshold value for the almost_full signal. When the amount of public data in the FIFO is greater than or equal to this value, the almost_full signal is activated;

Almost_empty_value

Integer

Non

Set the threshold value of the almost_empty signal. When the amount of data in the FIFO is smaller than or equal to this value, the almost_empty signal is activated;

Allow_wrcycle_when_full

Non

When scfifo is full, users are allowed to merge read/write cycles. The default value is off. This parameter is only valid when the overflow_checking parameter is set to on;

Intended_dvvice_family

Non

Set the device model to be used for functional simulation only.

1.3 Timing requirements

1. If the overflow protection circuit is set or the overflow_checking parameter is on, the wrreq signal is automatically ignored when the FIFO is full;

2. if either of the above two measures is not implemented, the wrreq signal cannot be matched during the same clock cycle when the FIFO is full, that is, wrreq cannot be increased during this period, the same applies when the FIFO is null.

3. The following two sequence diagrams are used for detailed description:

1.4 output status tag and latency

For dcfifo, the output latency is shown in:

1.5 avoid the impact of sub-Steady State 1.6 Synchronous Reset and Asynchronous Reset

In different modes, the effects of synchronous and asynchronous reset are different. scfifo supports synchronous or Asynchronous Reset. dcfifo supports Asynchronous Reset, And the reset signal is synchronized with the write clock. For specific effects, see table 3 (scfifo) and table 4 (dcfifo ):

Table 3 Effects of synchronous or Asynchronous Reset signals on different scfifo Modes

Mode

Synchronous Reset

Asynchronous Reset

Impact on status bit

Clear the full, almost_full flag

Activate empty and almost_empty

Reset the usedw flag;

Trigger point

Clock rising edge

Anytime

Effect on Q output in Normal Mode

If Q is not stored, the first data of scfifo is output; otherwise, the previous data is output;

Keep the previous data output;

Influence on Q output in pre-Read mode

If Q is not stored, keep the previous data output for a period of time, and then output the first data in scfifo after the next clock rising edge. If Q is not stored, keep the previous data output;

If Q is not stored, the first data of scfifo is output after the next rising edge of the clock; otherwise, the previous data is output;

Table 4 effects of Reset signals on dcfifo in different modes

Mode

Asynchronous Reset Signal

Asynchronous Reset signal synchronized with the write clock

Impact on status bit

Clear the wrfull flag

Before clearing the wrfull sign, set 1 to maintain the rising edges of the three clocks;

Clear rdfull flag

Activate wrempty and rdempty flag

Reset the wrusedw and rdusedw logos;

Effective trigger point

Anytime

Effect on Q output in Normal Mode

If Q is not stored, the output remains unchanged; otherwise, it is cleared;

Influence on Q output in pre-Read mode

If Q is not stored, an unknown value is output; otherwise, it is cleared.

1.7 different input/output bits

Dcfifo_mixed_widths supports setting the output data to different bit widths. In the FIFO parameter editor, you can select the input/output bit width ratio, which must meet certain requirements, different Input/output clock frequency ratios and different RAM types limit the selection of input/output bit width ratios. When you select a bandwidth ratio that does not meet the requirements, you cannot generate a FIFO.

The following is an example. For example, if the input data bit width is 16 bits and the output data bit width is 8 bits, the input/output clock frequency ratio should be. At the same time, after two clock periods are entered, that is, after two data records are input, the wrusedw flag value should be 2, and the rdusedw flag value should be 4, that is, after four output clock cycles without writing any more, the FIFO is read empty and the empty flag is activated. The Sequence Chart in this example is shown in:

Chapter 2 Design Example 2.1 design example Overview

In this design, data needs to be transferred from Rom to ram. Rom and RAM are independently driven by irrelevant clocks. At this time, dcfifo can effectively handle data exchange issues in asynchronous clock domains. The system diagram is as follows:

2.2 System Simulation Analysis 2.2.1 write operations

2.2.1.1 Initialization

Before 10 ns after system power-on, the reset signal is increased. Each module is initialized and the write controller is in the idle state. In the idle status, the write controller lowers the signal fifo_wrreq and requests data from the ROM address 00. The Rom is configured as the output non-storage mode, so the ROM data is directly transmitted to the FIFO write input without the reset signal. This reduces the data latent time, because rom_out is directly connected to fifo_in, which is the input port with storage on dcfifo.

2.2.1.2 write operations

If fifo_wrfull is invalid (low level) when the reset signal is low, the write controller enters the write state. The write controller increases the signal of fifo_wrreq and performs write operations. In the write state, the rom_addr value remains unchanged, so that the read data in the ROM remains stable for at least one write clock period before the first (the next write clock rising edge) is written to the FIFO.

2.2.1.3 address Switching

When the data in the Rom is not read, that is, when the rom_addr is smaller than FF, the write controller enters the incadr state after the write state. In the incadr state, the write controller lowers fifo_wrreq and increases rom_addr by 1. Until the data in the Rom is obtained.

2.2.2 Read operations

2.2.2.1 Initialization

At the beginning, the reset is valid. In this case, the fifo_rdempty signal is increased. In this case, ram_addr = ff. In this case, the address is incremented in the next state, so that the data in the ROM address 00 can be written at the address 00 in Ram.

2.2.2.2 write operations

When the next rising time of the clock arrives, the reset is invalid. When the fifo_rdempty is lowered, the read controller enters the incadr state from the Idle State. In the incadr state, the read controller increases the signal fifo_rdreq, read data from the FIFO and write it to ram.

2.2.2.3 write to ram

After incadr state, the read controller enters the write State. In the write state, the ram_wren and ram_rden signals are raised, so that Ram receives data from dcfifo data output Q and stores it in Ram.

2.2.3 when dcfifo is full

2.2.3.1 waiting status

When the write controller is in the incadr state and the fifo_wrfull signal is valid, the write controller enters the wait state when the next write clock rising edge arrives. In the wait status, the write controller maintains the value of rom_addr. If the fifo_wrfull signal continues to be valid, the write controller continues to maintain the wait status. When fifo_wrfull is invalid, the write controller enters the write status when the next write clock rising edge arrives.

2.2.3.2write status

When the write status is in the write state and the Rom has not been read blank, the write controller pulls the fifo_wrreq signal and the write controller enters the incadr state after the rising edge of the next write clock arrives.

2.2.4 complete data transfer from Rom to dcfifo

2.2.4.1done status

When the write controller is in the write state and rom_addr = ff, it starts to write the last data in the Rom to dcfifo. When the next write clock rising edge arrives, the write controller enters the done state.

2.2.4.2rom

In the done status, the write controller lowers the fifo_wrreq signal and does not enter the write operation status.

2.2.5 complete data transfer from dcfifo to ram

The analysis is similar to the 2.2.4 Summary.

Appendix FIFO configuration page: 1

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3

4

5

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Generate FIFO using quartuⅱ