Generation 335 project development record 7_28335 clock

Listen 335 clock

On the 335, there is an on-chip clock Module Based on the PLL circuit. 1 shows that there are two ways to provide clock for the CPU and peripherals:

One is to use an external clock source, connect it to the X1 pin or the xclkin pin, X2 grounding;

The other is to use an oscillator to generate a clock. A circuit consisting of a 30 MHz crystal and two 20pf capacitors is connected to the X1 and X2 pins respectively, and the xclkin pin is grounded.

We usually use the second method to generate a clock. This clock will be frequency doubled through an internal PLL Phase-lock circuit. The maximum frequency of f28335 is 150 m, so the maximum frequency is 5. The multiplier value is determined by the four lower bits of pllcr and the 7th and 8 bits of pllsts. For the detailed multiplier value, refer to Datasheet of generation 335.

Three clock input methods:

The initpll function called in the initsysctrl function is used to set the clock:

//---------------------------------------------------------------------------// This function initializes the PLLCR register.void InitPll(Uint16 val, Uint16 divsel){   // Make sure the PLL is not running in limp mode   if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)   {      // Missing external clock has been detected      // Replace this line with a call to an appropriate      // SystemShutdown(); function.      asm("        ESTOP0");   }   // DIVSEL MUST be 0 before PLLCR can be changed from   // 0x0000. It is set to 0 by an external reset XRSn   // This puts us in 1/4   if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)   {       EALLOW;       SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;       EDIS;   }   // Change the PLLCR   if (SysCtrlRegs.PLLCR.bit.DIV != val)   {      EALLOW;      // Before setting PLLCR turn off missing clock detect logic      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;      SysCtrlRegs.PLLCR.bit.DIV = val;      EDIS;      // Optional: Wait for PLL to lock.      // During this time the CPU will switch to OSCCLK/2 until      // the PLL is stable.  Once the PLL is stable the CPU will      // switch to the new PLL value.      //      // This time-to-lock is monitored by a PLL lock counter.      //      // Code is not required to sit and wait for the PLL to lock.      // However, if the code does anything that is timing critical,      // and requires the correct clock be locked, then it is best to      // wait until this switching has completed.      // Wait for the PLL lock bit to be set.      // The watchdog should be disabled before this loop, or fed within      // the loop via ServiceDog().  // Uncomment to disable the watchdog      DisableDog();      while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)      {      // Uncomment to service the watchdog          // ServiceDog();      }      EALLOW;      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;      EDIS;    }    // If switching to 1/2if((divsel == 1)||(divsel == 2)){EALLOW;    SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;    EDIS;}// If switching to 1/1// * First go to 1/2 and let the power settle//   The time required will depend on the system, this is only an example// * Then switch to 1/1if(divsel == 3){EALLOW;    SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;    DELAY_US(50L);    SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;    EDIS;    }}

If we want the DSP to work at a certain frequency, we can set the uint16 Val and uint16 divsel parameters.

To put it bluntly, it is equivalent to multiplication 10, except 2 (30*10/2 = 150 MHz)

For more details, refer:

Http://wenku.baidu.com/link? Url = vL0bh97ETShHDNcARicm11dkcvSac4VbUE-mm9uvkZSxq4wDpYi3x9Xxevtq7moLFlBX3KSYSQ6icRGo21ePg7MWfu8hI4cnfrn_aAFRUUi

Generation 335 project development record 7_28335 clock