Getting Started ARM compilation (i)--Knowledge paving

I read Shi Tiesheng prose, piecemeal involved in my life has not occurred in the memory, as the northern Huangshan thick soil in the sad xintianyou, those who can believe the same sunshine and the sun under the pious people. I want to have a long journey, in the fine flow of time and road, observing all the way of survival, and people among them. I found I fell in love with the north, China's north. Full of desolation of the breath: those chapped and barren loess, dry and anxious like veins generally extend the river bed, those skin black wrinkle like cypress old skin farmers ... People and the earth have a primitive and simple appearance, reflecting the ordinary history. --Seven years

Registers are used almost everywhere in the ARM assembler code, which is a high-speed storage unit used by the processor for staging instructions, data, and addresses. For example, a variable in a high-level language, in a compilation, whose value may be stored in a register.

The R0, R2, and SP in the code above are ARM registers.

There are 31 universal registers and 6 status registers for ARM processors. However, some of these are used in a single processor mode, including 15 general-purpose registers (R0 to R14), one or two status registers (CPSR/SPSR), and program counters (PC/R15).

R0 ~ R14 can be divided into two categories, namely: the Non-group register (R0 ~ R7) and the group register (R8 ~ R14). The so-called non-grouping, that is, the register in each processor mode share the same physical register, so-called grouping, that is, the register in different processor mode, corresponding to the different physical registers.

The Grouping register (R8 ~ R14) can be divided into two categories: (1) R8 ~ R12 has 2 sets of physical registers: 1 for FIQ mode, and 1 for all modes except FIQ. (2) R13 ~ R14 have 6 sets of physical registers, 1 groups for user mode and system mode, and 5 groups for 5 abnormal modes respectively.

In addition, R13 is commonly used as a stack pointer, called Sp;r14, as a link register, called LR. CPSR is the current program State Register, and SPSR is the program state Save register. When an exception occurs, SPSR is used to save the state of the CPSR.

Finally, the ARM processor uses a 3-level pipelining mechanism to speed up instruction processing. Therefore, the PC always points to the address of the next 2 instructions of the current instruction, that is, the current instruction address value Plus 8 bytes.

The ARM processor supports 7 modes of operation:

• User Mode (usr)
• Fast Interrupt mode (FIQ)
• External interrupt mode (IRQ)
• Management Mode (SVC)
• Data access termination mode (ABT)
• System Mode (SYS)
• No instruction Abort mode defined (und)

In addition to user mode, other modes are privileged mode, the processor can access protected system resources, and ARM program reverse analysis usually involves only user mode. In user mode, the processor can access R0 ~ R14, PC (R15), CPSR, and no SPSR.

The ARM processor has two operating states: (1) ARM status: 32-bit aligned arm instruction, and (2) Thumb state: Executes a 16-bit thumb instruction to it.

There are some differences in the names of the registers in both States, and only the different parts are listed below:

• The FP in the Thumb state corresponds to the R11 in the ARM state
• The IP in the Thumb state corresponds to the R12 in the ARM state
• The SP in the Thumb state corresponds to the R13 in the ARM state
• The LR in the Thumb state corresponds to the R14 in the ARM state
• The PC in the Thumb state corresponds to the R15 in the ARM state

The ARM assembly for the Android platform is compiled for the GNU arm, using gas (GNU ASSEMBLER,GNU Assembler).

Learning materials: "Android software security and reverse analysis"

Getting Started ARM compilation (i)--Knowledge paving