Hardware architecture of smart phones

With the continuous development of the Communication Industry, mobile terminals have evolved from a single call function to voice, data, images, music, and multimedia.

For mobile terminals, there are basically two types: feature phone and smart phone) smartphones have the basic functions of traditional mobile phones and have the following features: scalability of open operating systems, hardware and software and support for third-party secondary development compared with traditional mobile phones, with its powerful functions and convenient operations, smartphones have become increasingly popular and will gradually become a trend in the market.

However, as a portable and mobile terminal, the power supply relies entirely on batteries. As smartphones become more and more powerful, their power loss also increases, there are two solutions to this problem: one is equipped with a larger cell phone battery, and the other is improved system design, use advanced technologies to reduce power loss of mobile phones

At present, cell phones are mainly equipped with lithium-ion batteries, although the energy density of lithium-ion batteries has increased by nearly 30%, however, it still cannot meet the development needs of smartphones. For the lithium-ion battery materials currently used, the energy density only increases by about 20%, while the other is a fuel cell that is widely seen in the industry as the future development trend of mobile phone battery. This allows smartphones to talk for more than 13 hours, the standby time is up to one month, but this battery technology is still immature, and there is still a period from commercial use [1]. Increasing the battery capacity of mobile phones will increase the total cost of the entire device.

Therefore, starting with the overall design of the smart phone, the application of advanced technologies and devices to design a solution to reduce power loss, so as to extend the use time and standby time of the smart phone as much as possible, low-power design has become an increasingly urgent issue in smartphone design.

1. Smart phone hardware system architecture

The hardware architecture of the smartphone discussed in this article is a dual-CPU architecture, as shown in figure 1.

The main processor runs an open operating system and controls the entire system from the DBB (Digital Baseband Chip) where the processor is a wireless modem ), it mainly implements A/D conversion of voice signals, D/A conversion, encoding and decoding of digital voice signals, channel encoding and decoding, and timing control of wireless modem. Master-slave processors are used for communication through serial ports. XXX company CPU chip, it adopts the CMOS technology, has the arm926ej-s kernel, uses the AMBA (advanced microcontroller bus architecture) of arm company ), it contains 16 KB instruction cache, 16 KB data cache, and MMU (Memory Management Unit, with an optimized MPEG4 hardware codecs, you can perform hardware processing on MPEG4 coding/decoding and voice compression and decompression with a large amount of computing resources, this reduces the operational pressure on the ARM kernel. The main processor contains LCD (LCD) the Controller, camera controller, SDRAM and srom controller, many universal gpio ports, and SD card interfaces enable it to be well applied to the design of smart phones.

In the hardware architecture of smart phones, wireless modem only requires some peripheral circuits, such as audio chips, LCD, camera controllers, microphones, speakers, power amplifiers, and antennas, it is a complete hardware circuit used by ordinary mobile phones (traditional mobile phones) to simulate the communication between the baseband (ABB) Voice Signal pin and the audio codecs chip to form a voice channel during the call.

From the system architecture of this hardware circuit, we can see that the most power-consuming part includes the main processor, wireless modem, LCD and keyboard backlight, audio codecs and power amplifiers. Therefore, in the design, it is very important to reduce their power consumption.

2 Low Power Design

2.1 reduce the power supply voltage and frequency of the CPU

In digital integrated circuit design, the static power consumption of the CMOS circuit is very low, which is negligible compared with the dynamic power consumption. Therefore, the formula for calculating the dynamic power consumption is not considered as follows:

Pd = "ctv2f" (1)

Medium: Pd is the dynamic power consumption of the CMOS chip; CT is the load capacitance of the CMOS chip; V is the operating voltage of the CMOS chip; F is the operating frequency of the CMOS chip

According to Formula 1, the power consumption in the CMOS circuit is linearly related to the switching frequency of the circuit, and the power supply voltage is quadratic. For the CPU, the higher the vcore voltage, the faster the clock frequency, the larger the power consumption. Therefore, if the system performance can be properly met, select a low-voltage CPU as much as possible for the selected CPU, reduces the power supply voltage and frequency, and achieves better results in the overall power consumption.

For the main CPU, the kernel power supply voltage is 1.3 V, which is very small, and the clock speed during full-speed running can be set as needed, the other frequencies required internally are calculated by the frequency division to generate the main CPU clock speed FCPU. The formula is as follows:

On the COMs chip, in order to prevent damage caused by static electricity, unused pins cannot be left blank. Generally, the drop-down resistor is used to reduce the input impedance. To provide a load discharge path, a pull resistor is needed to increase the output level, this improves the noise tolerance of the chip input signal to enhance the anti-interference capability,
You must consider the following:

A) In terms of power consumption reduction and the chip's reverse irrigation current capacity, the pull-up resistance should be large enough to reduce the current;

B) To ensure sufficient driving current, the pull-up resistance should be small enough to increase the current;

C) in high-speed circuits, excessive pull-up resistance will smooth the signal edge and degrade the signal integrity.

Therefore, when considering the ability to drive the back-level normally (that is, taking into account the VIH or devil of the chip), select as much resistance as possible to save the power consumption of the system for the drop-down resistance, the situation is similar

2.3.2 handling of suspended pins

For the floating pins of CMOS devices in the system, attention must be paid to the input impedance of the CMOS floating input end, which is very high. It is very likely that some electric charges will lead to high-voltage breakdown of the device, in addition, it will also lead to random changes in the input signal level, causing the CPU to be continuously awakened during sleep, and thus unable to enter the sleep state or other inexplicable faults. So the correct method is, based on the initial state of the pin, the unused input is connected to the corresponding power supply voltage to maintain a high level, or to maintain a low level through grounding.

2.3.3 selection of Buffers

The buffer has many functions, such as level conversion, adding driving capabilities, and direction control of data transmission. When adding a buffer only based on driving capabilities, you must consider it with caution, because the driving current is too high, more energy is wasted. Therefore, we should carefully check whether the maximum output current of the chip is sufficient for the ioh and IOLs to drive lower-level chips, avoid using buffers when selecting appropriate front-and back-level chips.

Power supply circuit 2.4

Because the dual-CPU architecture is used and many peripherals are used, many types of power supply are required, namely 1.3 V, V, and V. Therefore, many voltage change units are required, there are several voltage conversion methods: Linear Regulator, DC/DC, and low-leakage regulator. The ldos is essentially a linear regulator, which is mainly used in scenarios with low pressure difference, so merge it into a Linear Voltage Regulator

A Linear Voltage Regulator features a simple circuit structure and requires a small number of components. The input and output pressure difference can be large, but its critical weakness is its low efficiency and high power consumption, its efficiency depends entirely on the output voltage.

The DC/DC circuit features high efficiency, flexible increase/decrease, but its disadvantage is that the circuit is relatively complex, the ripple noise interference is large, the volume is relatively large, and the price is higher than the linear voltage regulator, for boost, only DC/DC can be used. Therefore, in the design, DC/DC voltage converter is used for scenarios where the noise of Power Supply ripple is not strict, this effectively saves energy and reduces the power consumption of smartphones.

2.5 LED light control

In the smart phone circuit, the keyboard and LCD backlight consume a lot of energy when working, for example, the LCD used in this architecture, the electrical requirements of the backlight are as follows: the typical positive current value is 15 mA, the typical positive voltage value is 14.4 V, and the consumption power of the backlight is 216 mW.

It can be seen that the power consumption of LED lights on the LCD background is very high during normal operation. Therefore, to reduce the power consumption of LED lights, you can use the following methods:

A) a small resistor is transient in the LED lamp circuit to change the resistance value, which is used to control the current when the LED lamp is working.

B) Use PWM (Pulse Width Modulation) signals to control the switch of LED lights based on the lag effect of human eyes

In the main CPU, by configuring the register gpcon_u, gpcon_l can be gpio20 gpio23 and gpio2-gplo5 configured into the PWM signal output, and then configure the corresponding internal registers, control the PWM output signal frequency and duty cycle, the LED backlight is controlled as a control pin to reduce the power consumption of the LCD backlight.

C) provide an interface for adjusting the brightness of the backlight on the graphic interface of the mobile phone, so that you can further adjust the brightness of the backlight Based on the brightness of the LED lamp set by the system, it not only increases the flexibility of mobile phone usage, but also further reduces the power consumption of mobile phones.

2.6 wireless modem control

1. The hardware architecture of the smart phone uses a dual-CPU architecture, and the wireless modem is used as a peripheral of the main CPU. Compared with other peripherals of the main CPU chip, for example, when a smartphone is in sleep mode, the power supply of peripheral devices such as LCD and camera can be directly disabled, while wireless modem cannot. wireless modem must be required to continue waiting for incoming calls and searching for networks, instead of shutting it down directly, the wireless modem solution in the hardware architecture in this article also has a system with complete internal operation of GSM (Worldwide mobile communication systems) protocol and independent power management module, the main CPU can use the UART port and wireless modem for power management negotiation and control the internal power supply management reasons of the wireless modem. When the wireless modem is idle, you can enter and exit the standby mode in good condition. Therefore, in the design of the hardware architecture in this article, when the smart phone is started, power-on or power-off the wireless modem, and power-off the modem.

2.7 software optimization

Formula: M = mdiv + 8; P = pdiv + 2, s = sdiv; mdiv, pdiv, and sdiv can be set through registers.

Therefore, it is determined that the main CPU clock speed is a key factor for the power consumption and performance of the entire system. In this paper, the main CPU clock speed is set to 204 MHz based on the overall consideration of system performance and power consumption.

2.2 DPM

DPM (Dynamic Power Management) is used to reduce power consumption by dynamically controlling the clock or voltage of the system during system operation. This dynamic control is closely related to the running status of the system, this work is often implemented through software [34]

2.2.1 define different working modes

In the hardware architecture, the smart phone working mode is closely related to the working mode of the master CPU. To reduce power consumption, the master CPU defines four working modes: General clock gating mode; idle mode: sleep mode; when the master CPU clock speed is determined, four working modes are defined in the smartphone: normal and idle ); sleep and off modes are described as follows:

A) normal working mode: The main CPU uses the General clock gating mode, the main CPU runs at full speed, and the clock frequency is 204 MHz, depending on the running status, such as playing MP3, making phone calls, and actual measurement, the current of the smart phone is about 200 mA in this mode.

B) idle mode: the active CPU is in idle mode, and the active clock of the active CPU is stopped. The clock frequency is 204 MHz. When the idle mode is enabled, the keyboard backlight and LCD backlight are disabled, there is a standby screen on the LCD, and specific events can enable the smart phone to work in idle mode, such as clicking the touch screen, timed wake-up, buttons, incoming calls, etc.

C) sleep mode: the active CPU uses sleep mode. All the other functions are disabled except the wake-up logic inside the active CPU; the main CPU clock is a 36.768 kHz slow clock. In addition to the modem, all peripherals are disabled. Press the on key for a short time to enable the smart phone to wake up in sleep mode and go to normal working status.

D) shutdown mode: the master CPU uses the stop mode. In addition to the master CPU leakage current, no power is consumed. When the master CPU is disabled, the smart phone must be restarted before it can work normally, in actual measurement, the current of the mobile phone is 100 μA in this mode.

As we can see from the above, the power of a smartphone in normal working mode is much greater than that in idle mode and sleep mode. Therefore, when a user does not perform operations on the phone, it is set through software, enable the mobile phone to enter idle mode or sleep mode as soon as possible
When you perform operations on the mobile phone, wake up the master CPU through the corresponding interrupt, so that the mobile phone can return to normal working mode. After handling the response, the mobile phone quickly enters idle or sleep mode.

2.2.2 disable idle peripheral controllers and peripherals

In the architecture of the hardware system, we can see that the main CPU uses the corresponding interface to connect many external devices, such as LCD, camera, and IrDA (infrared adapter) bluetooth, audio codecs, power amplifiers, and other devices when the smart phone is in normal working mode, the idle Peripherals can be accessed through the gpio port of the main CPU, the control of the peripheral power supply of the LDC or DC/DC power chip, by disabling the peripheral Power Supply chip, in order to turn off the peripherals, especially for large power consumption peripherals, it must be reliably disabled for some working peripherals, such as audio codecs, by setting internal registers, disables channels, power amplifiers, and D/A converters that are not used inside the chip to reduce the power consumption of these devices during operation.

Generally, all interface controllers of the primary CPU are not used. Even if the smartphone is in normal working mode and in different running states, the usage of various interface controllers is different; the interface controller is not in the working state. If it is not closed, the current consumption will still be calculated. For the main CPU, the current consumption of each peripheral interface controller is as follows: NAND Flash is 2.9 Ma; LCD: 5.8 Ma; USB HOST: 0.4 mA; USB driver: 2.9 Ma; Timer: 0.5 mA; SDI: 1.9 mA; UART: 3.6 Ma; RTC: 0.4 mA; a/D converter is 0.4 mA; IIC is 0.6 mA; IIS is 0.5 mA; SPI is 0.5 mA

In the smart phone hardware architecture shown in figure 1, the SPI interface and USB host interface are not used. Therefore, you can disable the SPI and USB host interfaces permanently by setting the spcono and hccontrol registers, this saves 0.9 (0.5 + 0.4) Ma of current. When the smartphone is in normal working state, it can shut down the idle interface controller to further reduce the power consumption of the smartphone, it can also prevent the impact of reverse irrigation current on the bus.

2.3 Low Power Design of the interface Driving Circuit

When you choose a smartphone peripheral chip, such as SDRAM, LCD, camera, audio codecs, and other devices, in addition to considering its performance, the power consumption during normal operation must also be considered. When designing an interface circuit, the following factors must be taken into account:

2.3.1 selection of pull-up and drop-down Resistors

Software optimization is a very important task, which can greatly improve the efficiency of software operation and reduce the power consumption during software operation, such as command re-arrangement, without affecting the command execution result, the failure of the command line caused by loading delay, branch delay, and jump delay can be eliminated. [5] Arm Assembly shown in Table 1. After the instruction is converted to binary encoding, the difference is that the binary encoding of each register operand is different.

According to table 1, from the perspective of electrical performance, by reducing the Hamming distance between consecutive commands, the original code changes 6 times more than the bit of the optimized code, the two sets of code implement the same function. Therefore, the power consumption of the optimized command execution is less than the original command. Therefore, after the system software is complete, when the software functions are consistent, by optimizing the code, you can reduce the power consumption of the software during execution.

3. Test results and discussion

In the design of smart phones, the power loss of smart phones in idle and sleep modes is measured through continuous hardware optimization and dynamic management of power supply in software, the result is shown in table 2.

According to table 1, from the perspective of electrical performance, by reducing the Hamming distance between consecutive commands, the original code changes 6 times more than the bit of the optimized code, the two sets of code implement the same function. Therefore, the power consumption of the optimized command execution is less than the original command. Therefore, after the system software is complete, when the software functions are consistent, by optimizing the code, you can reduce the power consumption of the software during execution.

　　

As can be seen from table 2, after the optimization design, the current value of the smart phone in idle mode is reduced by 10.2 Ma, and in sleep mode, the current value is reduced by 1.5 Ma for wireless modem, because of its own independent power management module, it is basically about 3 Ma, and the changes are not much compared to the unoptimized design. After the smart phone is optimized, in sleep and Idle modes, the power loss has been significantly reduced, greatly improving the smartphone's standby time and use time under the same battery capacity. Therefore, the above method can effectively reduce the power consumption of the smartphone.
　
With the development of mobile phone technology, especially in the design of smart phones, low-power design will become an increasingly urgent problem. With the emergence of some new technologies and application in the design of smart phones, for example, advanced power management chips and advanced processors provide designers with greater flexibility, which can greatly reduce the power consumption of smart phones. However, as designers, in system design and software programming, we must always consider how to reduce the power consumption of the system. Only in this way can the designed system have a good performance, which is favored by users.