Hardware Design of Image Processing Platform Based on PCI Bus and DSP chip

Hardware Design of Image Processing Platform Based on PCI Bus and DSP chip

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Source: Electronic Technology Application Author: Kong Xianggang, Zhu Jing

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With the rapid development of computer, multimedia and data communication technologies, digital image technology has gained great attention and development in recent years, it has been widely used in scientific research, industrial production, medical and health, education, entertainment, management and communication. At the same time, people have higher and higher requirements on computer video applications, making high-speed, convenient, and intelligent high-performance digital image processing devices the development direction of video devices in the future, this requires the generation of new theories, new methods, and new algorithms. In order to verify the feasibility of using these new technologies, an image processing platform based on PCI bus and DSP chip is developed, the image processing platform is built using the video input processor SAA7113 of PHILIPS, the high-speed floating-point DSP of TI corporation and the S5933 PCI bus interface chip of AMCC Corporation. The high-speed PCI bus and powerful DSP Chips can be used to study algorithms such as video compression, image detection, and visual positioning.

1. Overview of system functions

The main functions of the system are as follows:

(1) automatic switch and processing can be performed between the PAL and NTSC of different input systems.

(2) It can use the acquired YUV image signal data to verify the compression algorithm, or convert it into grayscale image data, RGB Format Image Data for testing and locating algorithms.

(3) the processed data can be stored or further verified by the upper-layer system (PC) through the PCI interface.

(4) The system has software modification, upgrade, and flexibility, facilitating Algorithm Improvement and verification.

The main difficulty in system design is how to achieve high-speed transmission of system data. The image data is collected by the dedicated Integrated Video Decoder SAA7113. After A/D conversion, the data is transmitted to the DSP. After DSP processing, the data is transmitted to the PC through the PCI interface. How to achieve efficient data communication between SAA7113 and DSP and between DSP and S5933 is the key to solving this problem. Through analysis and research, the two frame rotation modes controlled by CPLD between SAA7113 and DSP are used to realize the line-by-line signal transformation of the image's line-by-line signal and synchronous acquisition and processing; the DMA transmission mode is used between DSP and S5933 to achieve high-speed transmission of data streams in the system to meet image processing requirements.

2 system hardware design

The entire system consists of video decoder, DSP and PCI bus dedicated chip. System diagram 1.

 

The DSP chip uses TMS320C32, Which is simplified based on TMS320C30 and contains the CPU core of TMS320C30. It adds some common functional components that enable Program guidance, serial interface transmission, and storage to support 8, 16, and 32-bit data. It can generate edge interruptions and level interruptions, and can be programmed by the user to set the address of the interrupt vector table. It has two power management modes: Empty wait and low power consumption. It has two DMA channels and powerful external memory interfaces, which can meet the requirements of 8-bit video decoding interfaces and implement high-speed data transmission of 32-bit PCI interfaces. The flexible program loading of TMS320C32 can be realized in system programming.

The dedicated interface chip for PCI bus uses S5933, which is a dedicated chip for PCI bus controllers with strong functionality and flexibility. The chip complies with the PCI local bus specification version 2.1, it can be used as the target device of the PCI bus to meet the basic transmission requirements. It can also be used as the PCI bus master device to access other PCI bus devices. The peak transmission rate of S5933 is 132 Mbps (32-bit PCI data line ). S5933 provides three physical BUS interfaces: pci bus interface, plus BUS interface (ADD-on bus), and optional NV memory interface. The user can design the logic circuit and configuration space initialization of S5933 connected to the plus bus interface as needed, without considering the many PCI Bus Specifications, in this way, the complex pci bus interface relationship is transformed into a simple 8/16/32-bit plus BUS (ADD-on bus) interface relationship. Function Diagram 2 of S5933 chip is shown in.

 

Data transmission between the PCI bus and the bus can be performed through three internal channels: first-in-first-out memory (FIFO), Mailbox register (Mailbox), and Pass-Thru. Each channel includes two sets of registers to complete two-way data transmission between the PCI bus and the ADD-ON bus interface, providing users with a loose and flexible design space.

The programmable video decoding chip uses SAA7113, which is a programmable video processing chip and uses CMOS technology. A simple I2C bus can be used to implement programming control. It contains two channels for Analog Processing, enabling video source selection and anti-aliasing (Anti-Counterfeiting frequency) filtering, modulus/number transformation, automatic embedding, automatic gain control, Clock generation, Multi-standard (pal bghi, pal m, pal n, ntsc m and ntsc n) decoding and brightness, contrast, and Saturation Control.

The system uses the software to simulate the I2C bus control mode, and implements DSP initialization and other control over SAA7113 through the DSP multi-function port. According to the synchronous pulse output by SAA7113, the programmable device CPLD is used, generates control signals such as address signal, read/write signal, and frame switching of image frame storage to implement high-speed data communication between SAA7113 and DSP.

3. seamless connection between DSP and SAA7113

SAA7113 outputs a line-by-line video signal. A frame of image needs to be transmitted twice, respectively, as an odd-Field Image and an even-field image. The video processing object is a line-by-line image signal, therefore, you must wait for an image (consecutive odd or even two signals) to be collected and then merged into an image frame for subsequent processing. Using the synchronous signal of SAA7113 and using the programmable logic device CPLD to construct a controller, image data can be written into the frame storage to solve the problem of image frame synthesis. To provide continuous image signals to the front-end processor (DSP), two image frame storages (A and B) are used to store the collected image data and the image data to be processed, real-time continuous acquisition and processing of images.

As shown in hardware interface 3 between DSP and SAA7113, the control logic of the entire interface includes two submodules: The frame image write controller and the ping-pong switch, which are completed by a CPLD. The CPLD chip uses the EPM9320RC208 of ALTERA. Two sets of frame storage devices A and B use two CY7C1049 CHIPS PRODUCED BY CYPRESS, with A capacity of KB × 8 bit. The access time does not exceed 15 ns and can meet the real-time image acquisition requirements.

 

SAA7113 is a digital video output port VPO [?] Output video data. The output data of SAA7113 is set to the standard ITU 656 YUV format. The data of each pixel is represented by two consecutive bytes. To facilitate the storage and processing of images, the system takes only 512x512 pixels in the middle of a frame as one frame, that is, the frame of the image is 512 rows in the center of the two consecutive even images, in addition, the image blocks in the middle of each line contain 512 pixels.

Using the synchronous signal of saa7113, the frame image is written into the Controller Module to generate the address signal, write signal, and one of the frame Switching signals (rdy1) of the frame memory ). The synchronous signals output by saa7113 include LLC, rts0, and rts1. LLC is the clock output of the row lock system, which is twice the pixel clock frequency, namely 27 MHz. It is used for synchronous data collection, so that a LLC cycle outputs one byte of image data. When the image data is valid, the rising edge is reversed as the we # signal of frame storage. The functions of rts0 and rts1 are determined by programming the saa7113 function register. Rts0 is set as a reference signal (valid line signal) for horizontal output. rts0 indicates that a valid line of pixels is collected at high power consumption, while rts0 indicates that a hidden field signal is acquired at low power consumption. After the rising edge of RTSO, write the frame image into the Controller to control the collection of 512 pixels in the middle of a row, and discard the remaining pixel data. Rts1 is set to vertical output reference signal and parity field signal. When rts1 is high, it usually indicates the valid data required to collect the odd field image. When rts1 is on the rising edge, it starts to collect the odd field image data, at the same time, it is also used as the signal to start the frame image; rts1 low power usually means to collect the image data required in the even field, and start to collect the even field image data when the rts1 descent edge. When the rising edge of rts1, the frame image is written into the Controller to control the acquisition of 256 rows of pixel data as an odd field image. When the falling edge of rts1, the following 256 rows of pixel data are collected sequentially as the even field image, the remaining image row data is discarded. With a 512 K x 8 bit static memory (SRAM), you can store a 512x2x8 bit image. When synthesizing an image, the nth pixel of the corresponding odd-field image and the nth pixel of the even-field image differ by 512 × 2 × 8bit in the memory, the frame image write controller uses the rts1 (parity field valid) signal as the A1 [11] In the frame memory address signal written into the image data. the counting output signal of the valid row in the field is used as the A1 [] in the frame memory address signal, and the counting output signal of the valid pixel in the row is used as the A1 [] in the frame memory address signal. in this way, the line-by-line signal is stored in an image frame memory. Figure 4 shows the sequence of synchronous signal acquisition. When a frame of image data is collected, the frame image is written into the Controller to generate the rdy1 signal, notifying the ping-pong switch.

 

A table tennis switch control module is constructed inside the CPLD to automatically switch between the two channels for reading and writing between frames. The address signal A1 [], write control signal WR # And saa7113 VPO [] generated by the frame image write controller constitute the starting interface of the image frame write channel; the address line signal A2 [], the read control signal R/W #, and the low 8-bit di [] of the Data Line constitute the terminal interface of the image frame read channel.; rdy1 and rdy2 (fx0) are used as frame switching readiness signals to trigger channel switching. When image data is collected, the frame switching readiness signals rdy1 and rdy2 are both false, the START interface signal of the image frame write channel is connected to the interface signals Rd, we #, a [] and D [] of image frame; the current frame image data of saa7113 is written to frame memory A. At the same time, the terminal interface of the image frame read channel is connected to the interface signal of image frame B, the DSP extracts the image data of the previous frame from frame B for processing. When the image data of the current frame is collected, the frame image is written into the Controller to stop the data collection and set rdy1 to true. Likewise, when the DSP completes processing the previous image, set the pin fxo to rdy2 to true. When the ping-pong switch module detects that rdy1 and rdy2 are both true, It switches the channel interface. At this time, the start interface of the image frame write channel is connected to the interface of image frame B; the current frame image data of saa7113 is written to Frame Memory B. The terminal interface of the image frame reading channel is connected to the interface signal of Image Frame Memory, the DSP extracts the image data of the previous frame from frame memory a for processing. In this way, two frames are rotated to achieve real-time continuous image processing.

The logic and time sequence conversion of all control signals between DSP and saa7113 are completed by CPLD, which increases the reliability, simplifies the layout of PCB, and can be modified by programming, improves the flexibility of use.

4. Interface Design Between S5933 and DSP

The three data transmission modes of S5933 have different characteristics and are used in different scenarios.

The S5933 mailbox mode does not support burst transmission. It consists of eight 32-bit mailbox registers and can be accessed in two directions. They are evenly divided into two categories, which are used for Bidirectional Information Transmission Between the PCI interface and the add-on interface. Both the host and extended logic can be queried or interrupted to learn the full status of any byte in any mailbox register, and access the byte through the corresponding address. The mailbox register of S5933 is mapped to the dsp I/O space, so that the DSP can perform direct operations on the mailbox at a low data rate, therefore, only commands and status information are transmitted in this way in the system. For example, a PC notifies the DSP device to shut down, and a DSP notifies the upper layer that the data has been transferred (the size of the processed data is not fixed.

The FIFO mode of S5933 is mainly composed of two 32 × 8-bit FIFO, read/write address registers and read/write counters shared by the two interfaces. The two FIFO instances serve as two-way buffers between the PCI and ADD-ON interfaces. S5933 provides shortcuts: a set of control and status signals specially used for FIFO transmission, including direct reading, writing, and status signals of FIFO registers, to improve data transmission speeds, however, this signal group can only work when S5933 is the master device. When S5933 is used as the target device, the internal FIFO is only used as the General Register. The PCI bus accesses them as the access mailbox register, and the operation is intuitive, but does not support burst transmission, the transmission speed is greatly limited. When S5933 is the master device, the FIFO mode can be used for DMA burst transmission, and S5933 can start the DMA transmission cycle through the FIFO interface, the transmission process does not require CPU intervention. The transmission rate is related to the data transmission rate of external devices, and a high data transmission rate can be obtained. There are two DMA data transmission start modes for S5933: PCI bus interface start and ADD-ON bus interface start. The start mode depends on which interface is used to set the read or write address registers and read or write counters. The start mode of the PCI bus interface is the PCI bus main device (usually the client program of the PC) set the DMA-related registers to initiate the DMA transmission. the ADD-ON bus interface is enabled by the external logic circuit (generally the cpu on the external plug-in card) and sets the DMA-related registers to initiate the DMA transmission.

The PASS-THRU method of S5933 allows the host to access the bucket of the ADD-ON Interface in memory ing mode. It can only work when S5933 is the target device, external interfaces are not commonly used because Logical Circuits are required.

This system is an experimental platform for image processing. It requires both high data transmission rate and certain upgrading functions and flexibility. Therefore, the system uses the FIFO data transmission mode. When the collected image data is large and requires high transmission speed, you can use the PCI bus interface in the FIFO mode to start the DMA mode and use DMA transmission. In some application scenarios, the number of data to be transmitted is unclear. For example, the data size after compression is not certain. You can use the bus interface to start the DMA transmission mode to transfer the compressed image, however, commands and image status information are transmitted in the mailbox. In this way, all the S5933 bus operation registers are mapped to the control signal IOSTRB # control space of the TMS320C32 DSP, the DSP can easily control the data transmitted by PCI interfaces, just like operating its own peripheral interfaces. The connection method of the hardware interface between S5933 and DSP is shown in Figure 5.

 

Hardware connection between S5933 and DSP, is to use the DSP's read/write signal R/W #, address selection control signal IOSTRB #, external device readiness signal RDY # And some address signals and S5933 FIFO Status Signal WRFULL for simple timing and logical combination, generate the read/write control signals for the S5933 bus interface: WR #, RD #, SELECT #, ADR [], BE [], and WRFIFO #. The S5933 Data Bus is connected to the DSP data bus. The data line width is 32 bits to provide the highest possible transmission rate.

This paper uses the PCI interface chip S5933, DSP chip TMS320C32 and video input processing chip SAA7113 to design and implement a video image processing experimental platform system that can achieve high-speed continuous acquisition of images, image compression, image processing and other algorithms are verified to achieve the system design goal. The system is flexible to use and easy to upgrade. Considering that the internal RAM of the DSP chip is limited, the program cannot run completely in the chip. When complicated image processing operations are performed, the speed is limited, therefore, this system is only applicable to static image processing algorithms.

 

References

1 Chen Lixue. Design of Microcomputer bus and interface. Chengdu] University of Electronic Science and Technology Press, 1998.6

2 TMS320 third-generation digital signal processor User Guide. Beijing] Beijing wenting Technology Development Co., Ltd., 1998

3 TMS320C3X Users' Guide. TI Inc, 2001

4 S5933 32-bit PCI MatchMaker Data Sheet. AMCC, 1998

5 SAA7113 9-bit Video Input Processor Data Sheet. Philips Semiconductors, 1999