Hardware settings for learning alicloud 0k6410

Recently, some network problems have led to a delay in blog writing. However, I have already used word on my computer.

OK. Go to the topic !!

After reading the video from Boss Wei, I learned that the numbers of the numbers and are different. In addition to shutting down the dog, I also need to set the hardware to tell the CPU which memory space we need. We can find it through the chip Manual

The above is the memory address of the from 0x00000000 ~ 0x6fffffff

1. Boot Image zone 0x0000_0000 ~ 0x07FF_FFFF

2. Internal Storage Zone

(1) internal ROM 0x0800_0000 ~ 0x0BFF_FFFF

(2) internal SRAM 0x0C00_0000 ~ 0x0FFF_FFFF

3. static storage zone 0x1000_0000 ~ 0x3FFF_FFFF

4. Dynamic Storage zone 0x4000_0000 ~ 0x6FFF_FFFF

 

The physical Memory of is divided into two parts: Memory and Pheriperal. The address ranges from 0 to 0 ~ 0x6fffffff and 0x7fffffff. System pass
The SPINE bus accesses the Memory space and the Pheriperal space through the PERI bus. In order to adapt to the access speed of different peripherals,
High-speed peripherals such as Camera and Accelerator access low-speed peripherals such as iic and watchdog through the APB bus.

3.2 memory
Memory, also known as the main Memory, is divided into four major areas: the starting image area, the internal Memory area, the static Memory area, and the dynamic Memory area.

The physical address of the starting image area is 0x00000000 ~ 0x07ffffff, 128 MB in total. The role of this region is used to start the system, as described in its name. However, there is no actual storage medium corresponding to this range. You can only select a specific start medium through om [] And then map the physical address of the corresponding medium to this start zone, for example, after the irom startup mode is selected, the address space occupied by irom is mapped to the space starting from 0x00000000.

The physical address of the internal memory zone is 0x08000000 ~ 0x0fffffff, 128 MB in total. This region corresponds to the internal memory address, and the internal ROM and SRAM are distributed in this interval. 0x08000000 ~ 0x0bffffff corresponds to the internal ROM. Of course, the internal ROM is not as many as 64 MB, and only 32 KB has the actual storage medium, which is a read-only zone, run the irom startup code. The first code that runs when irom is selected is bl0, Which is solidified by the manufacturer. 0x0c000000 ~ 0x0fffffff corresponds to internal SRAM. The actual available SRAM is 4 kb according to Samsung's manual. In fact, this is steppingstone for nandflash startup (but this steppingstone is 8 KB, which seems to be in conflict, I don't know if my understanding is incorrect ).

The physical address of the static memory area is 0x0000000 ~ 0x3fffffff, 6*128 MB in total. This area is used to access devices mounted on an external bus, such as SRAM, norflash, and onenand. This region is divided into six banks, each of which is 128 MB, and the data width can be up to 16 bits. Each bank is determined by xm0cs. Unlike S3C2410, bank2 ~ Bank5 can be mapped to nandflash, CF, and other non-linear memory. This does not mean that it can be implemented through bank2 ~ The bank5 address segment can directly access the internal addresses of nandflash and CF. On the contrary, the addresses of these banks cannot be used when mapped to these devices, the access to these non-linear memory still needs to be performed through the AHB Bus of the pheriperal space, which is the same as the access method in the S3C2410. However, when xm0cs2 is mapped to nandflash, steppingstone's 4 kb (or
8 K ?) The SRAM is mapped to the 4KB at the beginning of bank2, and when it is started in nandflash mode, bank2 is mapped to the place starting from 0x00000000. In fact, Steppingstone is mapped to 0x0000000, this is similar to the S3C2410 situation.

The physical address of the dynamic memory area is 0x40000000 ~ 0x6fffffff, 3*256 MB in total. The first MB is the reserved zone, and the actual dynamic memory zone is 0x50000000 ~ 0x6fffffff is divided into two intervals, accounting for 256 MB respectively. You can select two intervals through Xm1CS [0-1] of DMC. This memory Zone mainly refers to the extended DRAM, which can be up to MB of DRAM.

After learning about the storage structure, you can set it. The following is the peripheral address.

 

The code for setting the peripheral address is as follows: Tell the CPU

LDR R0, = 0X70000000

ORR R0, R0, #0X13

MCR P15, 0, R0, C15, C2, 4 // 256 M (0X70000000-0X7FFFFFFF)