Head. asm module documentation

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Head. ASM module documentation
By Jiang <Jiang>
E-mail: jznsmail@tom.com
Http://blog.csdn.net/jznsmail
1. Module Introduction
============
This module is the first code to be executed in protection mode.
Initialize each register, check whether the A20 gate is enabled, and jump to the main function to continue execution.

2. module functions
============
1. New register settings for each segment
2. Set the stack
3. Check whether A20 gate is enabled
4. Set a new global descriptor.
5. Set the Interrupt Descriptor
6. Set the paging Mechanism
7. Jump to main function execution

3. Related Concepts
============
1> 8259a Interrupt Controller
A 8259a chip has a total of IRQ signal lines: irq0 ~ Irq7, 8 in total. In PC,
There are two 8259a chips in total. by connecting them for use, there will be irq0 ~ Irq15, a total of 16 interrupt Signals
Line, each external device uses one or more external devices share one interrupt signal line, they are sent through IRQ
Send the interrupt request. After the 8259a chip receives the interrupt request, it selects the priority of the interrupt and then
The interrupt with the highest priority is processed, and the corresponding interrupt vector is sent to the CPU data.
Thread, and notify the CPU to be interrupted.
The CPU can handle a total of 256 types of interruptions. The CPU only provides one interface for other modules.
256 Interrupt Processing vectors, also known as interrupt numbers, are used by these interrupt controllers themselves
One of them interacts with the CPU. When you need to process it, you only need to tell the CPU which interrupt you are using
No.
There are two 8259a chips in the PC machine. Two chips work in cascade mode. One is the master chip and the other is the slave chip,
The Int port of the slave slice is connected to the irq2 of the master slice. The master slice is accessed through ports 0x20 and 0x21, while the slave slice is connected
Access through the 0xa0 and 0xa1 ports.
When the BIOS initializes the PIC, irq0 ~ Irq7 is allocated 0x8 ~ 0xf interrupt number, however, when the CPU
0x8 ~ The 0xf interrupt number is used by the CPU to handle errors.
The process is completed by sending a series of ICWs (initialization command words) to the corresponding port.
Each of the four ICWs has its own unique format and must be sent in order and must be sent
Port.

Icw1: sent to port 0x20 (main chip) 0xa0 (slave chip)
7 6 5 4 3 2 1 0
+ --- +
| 0 | 0 | 0 | 1 | M | 0 | c | I |
+ --- +
I-bit: 0 indicates that icw4 will be sent
C-bit: Clear 0 indicates that the work is in the cascade Environment
M-bit: indicates the level trigger mode of the interrupt request. In PC, set 0 to indicate "edge trigger mode"

Icw2: sent to port 0x21 (master chip) 0xa1 (slave chip)
7 6 5 4 3 2 1 0
+ --- +
| A7 | A6 | A5 | A4 | A3 | 0 | 0 | 0 |
+ --- +
Icw2 is used to indicate the interrupt of irq0, because the last three bits are all 0, therefore, the irq0
The interrupt number must be a multiple of 8.

Icw3: sent to port 0x21 (master chip) 0xa1 (slave chip)
Icw3 is sent only when the cascade operation is performed. It is mainly used to establish a connection between two PIC nodes.
The main and slave slices have different structures.
Main part structure:
7 6 5 4 3 2 1 0
+ ---- +
| Irq7 | irq6 | irq5 | irq4 | irq3 | irq2 | irq1 | irq0 |
+ ---- +
Above, if the corresponding bit is set to 1, the corresponding IRQ line will be used to connect to the slave segment. If it is cleared, the table
Indicates that the device is connected to the peripheral device.
Slave part structure:
7 6 5 4 3 2 1 0
+ --- +
| 0 | 0 | 0 | 0 | 0 | IRQ |
+ --- +
The IRQ bit indicates which IRQ of the master chip is connected to the slave chip, which must be the same as the one sent on the master chip.
The main part has the same structure.

Icw4: sent to port 0x21 (master chip) 0xa1 (slave chip)
7 6 5 4 3 2 1 0
+ --- +
| 0 | 0 | 0 | 0 | 0 | 0 | EOI | x86 |
+ --- +
X86 bit: Set the bit to work in the 80x86 architecture
EOI bit: if it is set to a bit, it indicates automatic termination. This parameter must be cleared on the PC.
Note:
If EOI is set to a bit, the chip automatically clears the corresponding bit in ISR. If EOI does not
If a location is set, the processing program needs to interrupt the processing program and send the EOI message to the chip.
The corresponding bits in ISR are cleared.

OCW Operation Command
They are used to control the priority of 8259a operations, interrupt blocking, and interrupt termination.
Ocw1: interrupt shielding, sent to 0x21 (master chip) 0xa1 (slave chip) Port
7 6 5 4 3 2 1 0
+ ---- +
| Irq7 | irq6 | irq5 | irq4 | irq3 | irq2 | irq1 | irq0 |
+ ---- +
If the corresponding bit is set to 1, the corresponding IRQ request is blocked.

Ocw2: Priority Control and interrupt end command, sent to 0x20 (master) 0xa0 (slave) Port
7 6 5 4 3 2 1 0
+ --- +
| R | SL | EOI | 0 | 0 | L2 | L1 | l0 |
+ --- +
EOI is also a type of ocw2 command. When The EOI bit is set to 1, this is an EOI message. Sl is specified
Level bit. If Sl is set, it indicates that this is an EOI message of a specified level. This message can be specified
Which bit in ISR is cleared, that is, the IRQ interrupt processing end. l2, L1, and l0 are used to specify
IRQ Number. in practical use, we set SL, L2, L1, and l0 to zero.
If Sl is set to zero, it indicates that this is an unspecified EOI message, then the 8259a chip automatically
The highest priority is cleared in the IRQ, because it is an interrupt that is being processed and waiting for processing.
The highest level is the interrupt that the CPU is processing.
When R is 0, it indicates that this is a fixed priority method. irq0 is the highest and irq7 is the lowest. When R is 1, the table
This indicates a cyclic priority. For example, if you specify ir2 as the lowest priority, the priority order is irq2 <irq3 <
Irq4 <... <irq7 <irq0 <irq1, that is, if IRQ (I) is the lowest, IRQ (I + 1) is the highest.

Ocw3:
7 6 5 4 3 2 1 0
+ ---- +
| 0 | esmm | SMM | 0 | 1 | p | ar | RIS |
+ ---- +

2> 8259a programming in IA-32 Architecture
The CPU allocates different interrupt numbers to different interrupts to identify each interrupt.
One Interrupt number corresponds to one interrupt service program. When an interrupt arrives, the processor uses
The interrupt number is used as the index. The entry address corresponding to the index in the Interrupt Descriptor Table is
The endpoint address of the interrupted service program. After the processor obtains the endpoint address, it jumps to this address for execution interruption.
Service Program.
Each table item in the Interrupt Descriptor Table (IDT) is an Interrupt Descriptor, and each Interrupt Descriptor contains
The address of an interrupted service program.
Interrupt Descriptor structure:
+ ------------------------------ + --- + ----- + --- + -------- +
| Offset 16-31 | p | DPL | 0d110 | 000 | reserved | 4
+ ------------------------------ + --- + ----- + --- + -------- +
31 1615 141312 87 54 0
+ ------------------------------ + -------------------------- +
| Segment selector | offset 0-15 | 0
+ ------------------------------ + -------------------------- +
31 1615 0
P: set table 1. This descriptor can be used.
DPL: privileged

The system loads the Interrupt Descriptor Table through the Interrupt Descriptor Table register (idtr ).
Structure:
+ --------------------------------- + ---------- +
| Base address | limit |
+ --------------------------------- + ---------- +
47 1615 0

4. memory image
============
+ --------------- +
|... |
+ --------------- +
| Kernel. c |
+ --------------- + 0x6000
| Gdt table (2 kb) |
+ --------------- + 0x5800
| IDT table (2 kb) |
+ --------------- + 0x5000
| PAGE table page3 (4 kb) |
+ --------------- + 0X4000
| PAGE table page2 (4 kb) |
+ --------------- + 0x3000
| PAGE table page1 (4 kb) |
+ --------------- + 0x2000
| PAGE table page0 (4 kb) |
+ --------------- + 0x1000
| Page Directory table (4 kb) |
+ --------------- + 0x0000