How can we accelerate the EDA tool of Altera? (IC design) (Quartus II)

Abstract
The speed of Altera's EDA tools is very slow. This article proposes some suggestions to accelerate Altera tools.

Introduction
The whole product of Altera is slow in several places:

1. interval of us II.
2. the timeout time of the niosii.
3. the upload time of the image builder.

There are several suggestions to speed up the period between us II and niosii.

1. Use the fastest CPU
The memory program works together with the CPU speed. Adding Ram and HD is not useful.

2. Do not use low-power and ultra-low-power CPUs
For example, if you are using Nb, daily devices or tablet computers will often choose low-power devices (such as l7500, with a power of about 17 W) or ultra-low (u7500, a cpu with a power of about), with a low power consumption and a low power consumption, but a low power consumption point means slow speed. If you need to program frequently, select the CPU (for example, t7500, power of about 35 W) of the specified power supply ).

3. Use the latest Quartus II version.
I know that many people are still using Quartus II 6.x, but not Quartus II 7. X has made a lot of improvements in the processing speed. It is the root cause of my experience. Originally, in the case that Quartus II 6.1 was about to have 2 points of attention, it takes only 1 minute to 30 seconds to reach Quartus II 7.2 SP1, and the speed increases significantly.

To speed up the dynamic time of the system builder, this is due to the I/O problem. It has little to do with CPU, mainly because of hard drive speed.

1. Use a kubernetes hard drive
For example, 7200 Tib or 10000 Gb/s hard disks, or SSD. Many Nb-configured hard drives are still 5400 hard drives. If the SSD cell is too high, 7200 hard drives are a good choice.

2. Use supercache II
Supercache II is a cache entity. If you have a large amount of RAM, such as 4 GB or above, we recommend that you open 1 GB to supercache II. This is the first time that you compile the system based on the FPGA builder, those controllers will be quickly retrieved from Ram by supercache II. The second time they will be uploaded to the later line. The reason is that the controllers are all in Ram, And the runtime will be shorter.

3
When you import an image to the system, the system searches for the following four channels [1]:
1. c: \ Altera \ 72 \ IP \ sopc_builder_ip \. The controller configurations provided by Altera are stored in this project.
2. c: \ Documents ents and Settings \ oomusou \. altera. altera_ip.ini under Quartus \, in which oomusou is the user name. This case shows the path searched when the system builder is imported, you can modify it in the IP search path of tools> options in the system builder.

 

Fig.1 FPGA builder IP search path

3. Search for the IP address under the case.
4. Search for the path recorded in the altera_ip_search_path system changes.

If a controller with the same name exists, the first permission is 1> 2> 3> 4.

If you want to accelerate the activation of the system builder, if you want to accelerate the activation of the System Builder with less than one to four search paths, you can accelerate the activation of the system builder.

1 is the security router interface of the controller configured in the FPGA builder, so nothing can be optimized. 3 is the IP address used in the case, so I can't talk about it. The relationship lies in 2 and 4.

Check your altera_ip_search_path system changes and whether you have logged on to the unnecessary route. Generally, if you only want to install Quartus II 7.2, otherwise, the system changes. If you have installed the latest version of Quartus II, this system changes because it is compatible with the Quartus II release version.

Altera_ip.ini is the biggest culprit in the time when the system uploads an image through the system.
C: \ Documents ents and Settings \ oomusou \. altera. the original purpose of Quartus \ altera_ip.ini is to allow you to set your own component library so that different projects can reuse this component from the perspective of engineering, it will be able to significantly shorten the development time, without having to re-create a sub-account every time, and the component of the certificate will also be credible in terms of product quality.

The problem is that when you use the component editor to create a new component, you will automatically add a search path to altera_ip.ini, as shown in the following figure:

Fig.2 FPGA builder IP Search Path 2

If you develop a lot of programming programs that are not Component Library, altera_ip.ini will still leave these paths, as a result, during the import process, the system must upload and update the system. This is the reason why the application of the system builder slows down.

The solution is to manage your altera_ip.ini case, and only place the component library path in altera_ip.ini, removing unnecessary paths, if the component is used in the case, place it in the IP address of the case. You do not need to modify the component in altera_ip.ini. This operation also has a good effect:

1. The system does not parse components unrelated to the current case.
2. If you want to modify the component, you will not accidentally change it to the component in other cases.
3. If you want to allocate the case to other computers, you do not need to set altera_ip.ini. The system can automatically import the file to the system.

Conclusion
This is a bit of my experience using the Altera EDA tool. If you are also excited about the speed of running the Altera tool, these suggestions should be helpful to you.

Remark
In fact, Altera still has no room for such EDA tools, and the popularity of core CPU is so popular now. However, due to the fact that Altera's tools are at the core of the middleware, the CPU usage is only 50%, but the kernel is not optimized yet. Let's take a look at the 7zip tool. As a result, the kernel is supported, and the CPU usage of each core is close to 100%, however, the speed is greatly improved, but currently the EDA tools of Altera have not been implemented yet.

See also
(Formerly known as us II)

Reference
[1] Quartus II help version 7.2: About FPGA Builder