These two days to modify the NIC driver to achieve 10/100/1000m adaptive, so study the next PHY chip and EMAC drive how compatible with 10/100/1000m network environment, recorded here.
The device-side data link layer in the network consists of a Mac chip and a PHY chip, and the PHY chip is automatically negotiated and configured according to the external network environment, and the MAC is configured according to the PHY state to achieve the coordination between PHY and Mac.
Now the mainstream NIC PHY chip is 100M and 1000M, are backwards compatible. The 100M PHY supports the 10/100m environment and the 1000M PHY supports the 10/100/1000m environment.
First of all, 10/100/1000m refers to the data transmit and receive rate, the unit is bps. So this is going to be done from the Mac and PHY's data-receiving interface.
Mac and PHY mainstream data interface has gmii MII rmii and so on. The number of data transmission lines is defined in the interface specification. The interface definition can see this article:
http://blog.csdn.net/skyflying2012/article/details/8252843
Taking Gmii/mii as an example to study, Gmii is 8 rx/tx lines, MII has 4 rx/tx lines.
First, the 100Mphy chip is connected to research. PHY is automatically negotiated with the outside network environment to determine its own speed. The 100M PHY supports the Mii interface, so the Mac side needs to be connected to the PHY with the Mii interface definition.
The most important thing is to provide the correct data clock to ensure the correct sampling and sending data.
For 100M PHY, this problem is solved because the Mii interface supports the 10/100m,4 root data cable, which only requires the Mac to provide a 2.5/25mhz data clock to the PHY.
The most interesting thing to consider is how to adapt to the 10/100/1000m network environment when the external 1000M PHY is used.
First, this is a backward process, first of all to see how PHY handles 10/100m and 1000M environments. The interface mode of the Mac and the clock are then configured according to the PHY configuration.
Randomly looking for a 1000M PHY chip datasheet,rtl88e1111, the description of the Gmii/mii interface is as follows:
According to this description, the Gmii interface mode supports the 1000M environment, but in the 10/100m environment, the PHY completion auto-negotiation is determined to be 10/100BASE-TX after the switch to the MII mode, the GMII PIN is compatible with MII (Mii 8 data lines have 4), The GMII interface definition has 2 CLK lines, GTX_CLK tx_clk (gmii/mii Rx CLK is provided by PHY), GTX_CLK provides GMII in 125MHZ,TX_CLK mode, 2.5/25mhz in Mii mode. A diagram of the hardware circuit for Mac and 1000M PHY is given below.
It can be seen that for 1000M PHY,GTX_CLK TX_CLK all need to be connected to the Mac, in the 10/100/1000m environment, I use oscilloscope to measure CLK is indeed said as above.
In conclusion,
For 100M PHY, external network 10/100m switch, only need to change the data clock provided by Mac, Mac interface mode is not changed, because Mii is compatible with 10/100m.
for 1000M PHY, the external network 10/100/1000m switch, the first need to change the Mac interface mode (using different number of data lines), because the 10/100m PHY will switch to MII mode, according to the interface mode is changing its data clock.
Of course, after auto-negotiation, PHY is the hardware logic to complete the conversion of mode Gmii/mii, and for Mac, it is up to the driver to determine the Mac's interface mode and the CLK to be supplied based on the working state of the PHY.
This is where our software developers most need to focus, depending on the state of the PHY, how to configure the Mac (interface mode data clock) to ensure consistency with PHY.
Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.
How Mac and PHY enable network adaptation
