Not much understanding of the FPGA global Clock, thus reprinted a document:
At present, synchronous sequential circuits are generally recommended for large designs. The synchronous sequential circuit is based on the design of Clock trigger, which puts forward higher requirements for clock cycle, duty ratio, delay and jitter. In order to meet the requirements of synchronous timing design, the design of the master clock is generally driven by the global clock resource in FPGA design to achieve the lowest clock jitter and delay. The FPGA global clock resource is typically implemented using a full copper layer process, and a dedicated clock buffer and drive structure is designed to minimize latency and jitter for all configurable units (CLB), I/O units (IOB), and selective block RAM (Block Select RAM) within the chip. To accommodate complex designs, the number of dedicated clock resources and digital delay phase-locked loops (DLLs) that are integrated in Xilinx's FPGAs is increasing, and the latest Virtex II devices can provide up to 16 global clock input ports and 8 digital clock management modules (DCM).
I. Xilinx device primitives related to global clock resources
Common Xilinx device primitives associated with global clock resources include: IBUFG, Ibufgds, BUFG, BUFGP, BUFGCE, Bufgmux, Bufgdll, and DCM, as shown in 1.
1. IBUFG is the input global buffer, which is the head global buffer connected to the dedicated global clock input pin. All signals entered from the global clock pins must pass through the IBUFG unit, otherwise the layout will be routed with an error. The IBUFG supports IO standards in many formats, such as AGP, CTT, GTL, GTLP, Hstl, LVCMOS, LVDCI, LVDS, LVPECL, LVTTL, PCI, Pcix, and SSTL.
2. The Ibufgds is a differential form of IBUFG, and when the signal is entered from a pair of differential global clock pins, the IBUFGDS must be used as the global clock input buffer. IBUFG supports IO standards in various formats such as BLVDS, LDT, Lvdsext, LVDS, Lvpecl, and Ulvds.
3. The BUFG is a global buffer, its input is the output of the IBUFG, the output of the BUFG reaches the IOB, CLB, selective block ram of the FPGA, and the minimum jitter of the clock delay.
4. The BUFGCE is a global buffer with a clock-enabled end. It has one input I, one enable end CE and one output o. Only when the BUFGCE CE is active (high) is the BUFGCE output.
5. Bufgmux is the global clock selection buffer, it has I0 and I1 two inputs, one control side s, and one output o. When S is low, the output clock is I0, and vice versa is I1. It should be noted that the application of Bufgmux is very flexible, and the I0 and I1 two input clocks can even be asynchronous relationships.
6. BUFGP equals IBug plus BUFG.
7. The Bufgdll is a global buffered delay phase-locked loop, which is equivalent to the combination of BUFG and DLLs. Bufgdll is often used in early design to perform functions such as synchronizing and driving the global clock. With the increasing improvement of the digital clock Management Unit (DCM), the current application of Bufgdll has been gradually replaced by DCM.
8. DCM is the digital clock Management unit, which mainly completes the clock synchronization, phase shift, frequency division, octave and Jitter and so on. DCM is inextricably linked to the global clock, and in order to achieve minimal latency and jitter, almost all DCM applications use global buffering resources. DCM can be generated directly from the Architecture Wizard in Xilinx Ise software.
Second, the use of global clock resources (five kinds)
How to use 1:IBUFG + BUFG:
IBUFG the method behind connecting BUFG is the most basic method of global clock resource usage, because IBUFG combination BUFG is equivalent to BUFGP, so this method of use is also known as the Bufgp method.
2. How to use Ibufgds + BUFG:
When the input clock signal is a differential signal, the IBUFGDS is used instead of the IBUFG.
3. How to use IBUFG + DCM + BUFG:
This method of use is the most flexible and is more effective in controlling the global clock. The DCM module can not only synchronize the clock, Phase shift, frequency division and octave, but also the output of the global clock can achieve jitter-free delay.
4. How to use Logic + BUFG:
The BUFG can not only drive the output of the IBUFG, but also drive the output of other common signals. When a signal (clock, enable, fast path) is very large and requires a minimum jitter delay, BUFG can be used to drive the signal, making the signal take advantage of the global clock resource. However, it should be noted that the input of ordinary IO or ordinary on-chip signal into the global clock wiring layer needs an intrinsic delay, generally around 10ns, that is, ordinary IO and ordinary on-chip signals from the input to the BUFG output has a natural delay of about 10ns, but the output of BUFG to all units on-chip (IOB, The delay of CLB, selective block RAM) can be ignored as "0" ns.
5. How to use Logic + DCM + BUFG:
DCM can also control and transform the normal clock signal, that is, the DCM input can also be a common on-chip signal.
Iii. considerations for using Global clock resources
The important principle that the global clock resource must meet is that the sufficient and necessary condition for using IBUFG or IBUFGDS is that the signal is entered from the dedicated global clock pin. In other words, when a signal is entered from the global clock pin, whether it is a clock signal or not, the IBUFG or ibufgds must be used, and if the IBUFG or Ibufgds hardware primitive is used for a signal, the signal is necessarily entered from the global clock pin. If you violate this principle, you will get an error when laying out your cabling. The use of this rule is determined by the internal structure of the FPGA: the inputs of the IBUFG and Ibufgds are physically connected only to the chip's dedicated global clock input pins, and are not physically connected to normal IO and other internal CLB. In addition, because BUFGP is equivalent to IBUFG and BUFG combination, the use of BUFGP must follow the above principles.
Four, the global clock resources of the example of the method
There are roughly two ways to instantiate a global clock resource:
The first is to instantiate the global clock resource directly in the program;
Second, the use of global clock resources is realized through the integration of phase constraints or the implementation of phase constraints;
The first method is simpler, and the user simply writes the code or draws a schematic based on the basic usage of the 5 global clock resources previously described.
The second method is to complete the call to the global clock resource by combining the constraints of a phase or implementation phase, which differs depending on the combination tool and the layout and routing tool.
How Xilinx FPGA global clock and global clock resources are used