How is division implemented in FPGAs?

Excerpt from: "Xilinx FPGA Development Practical Tutorial"

1) The dividend is repeated minus the divisor until the remainder is detected less than the divisor, the advantage: for the divisor and the divisor is small difference in the case of the appropriate

2) by the way of the chip to achieve the + state machine. Advantages: Very good way to implement your own hardware

3) through the FPGA-based DSP implementation, that is, direct use of "/", Advantages: fast speed

4) IP Core with FPGA

How is division implemented in FPGAs?