How is the oemaddresstable memory ing table used by wince?

Source: Internet
Author: User
  1. ;------------------------------------------------------------------------------
  2. ;
  3. ; File: memory_cfg.inc
  4. ;
  5. ; This file is used to define g_oaladdresstable. This table is passed
  6. ; Kernelstart To estabilish physical to virtual memory mapping. This table
  7. ; Is used also in iomem oal module to map between physical and virtual
  8. ; Memory addresses via oalpatova/oalvatopa functions.
  9. ;
  10. ;------------------------------------------------------------------------------
  11. ; Export Definition
  12. Export g_oaladdresstable [Data]
  13. ;------------------------------------------------------------------------------
  14. ;
  15. ; Table format
  16. ; Cached address, physical address, size
  17. ;------------------------------------------------------------------------------
  18. G_oaladdresstable
  19. DCD 0x80000000, 0x30000000, 64; 32 mb dram Bank 6
  20. DCD 0x84000000, 0x10000000, 32; ngcs2: PCMCIA/pccard
  21. DCD 0x86000000, 0x18000000, 32; 32 MB srom (SRAM/ROM) Bank 3
  22. DCD 0x88000000, 0x20000000, 32; 32 MB srom (SRAM/ROM) Bank 4
  23. DCD 0x8a000000, 0x28000000, 32; 32 MB srom (SRAM/ROM) Bank 5
  24. DCD 0x8c000000, 0x08000000, 32; 32 MB srom (SRAM/ROM) Bank 1
  25. DCD 0x90800000, 0x48000000, 1; memory control register
  26. DCD 0x90900000, 0x49000000, 1; USB Host register
  27. DCD 0x90a00000, 0x4a000000, 1; interrupt control register
  28. DCD 0x90b00000, 0x4b000000, 1; DMA control register
  29. DCD 0x90c00000, 0x4c000000, 1; clock & Power register
  30. DCD 0x90d00000, 0x4d000000, 1; LCD control register
  31. DCD 0x90e00000, 0x4e000000, 1; NAND Flash control register
  32. DCD 0x90f00000, 0x4f000000, 1; camera control register
  33. DCD 0x91000000, 0x50000000, 1; UART control register
  34. DCD 0x91100000, 0x51000000, 1; PWM timer register
  35. DCD 0x91200000, 0x52000000, 1; USB device register
  36. DCD 0x91300000, 0x53000000, 1; watchdog timer register
  37. DCD 0x91400000, 0x54000000, 1; IIC control register
  38. DCD 0x91500000, 0x55000000, 1; IIS control register
  39. DCD 0x91600000, 0x56000000, 1; I/O port register
  40. DCD 0x91700000, Zero X 57000000, 1; RTC control register
  41. DCD 0x91800000, 0x58000000, 1; A/D convert register
  42. DCD 0x91900000, 0x59000000, 1; SPI register
  43. DCD 0x91a00000, 0x5a000000, 1; SD interface register
  44. DCD 0x92000000, 0x00000000, 32; 32 MB srom (SRAM/ROM) Bank 0
  45. DCD 0x00000000, 0x00000000, 0; end of table
  46. ;------------------------------------------------------------------------------
  47. End

In the past, I never knew what was going on with this table. I had a chance to call his function.

C: \ wince500 \ platform \ common \ SRC \ Arm \ common \ Memory. c

  1. //------------------------------------------------------------------------------
  2. //
  3. // File: memory. c
  4. // The code shows the relationship between the arm virtual memory and the physical memory.
  5. // Memory interface routines.
  6. //
  7. # Include <windows. h>
  8. # Include <oal_log.h>
  9. # Include <oal_memory.h>
  10. Typedef struct {
  11. Uint32 CA; // cached virtual address
  12. Uint32 Pa; // physical address
  13. Uint32 size; // size, in MB bytes
  14. } Oal_address_table, * poal_address_table;
  15. //------------------------------------------------------------------------------
  16. //------------------------------------------------------------------------------
  17. //
  18. // Function: oalpatova
  19. //
  20. // Converts a physical address (PA) to a virtual address (VA). This routine
  21. // Uses the oemaddresstable defined in the platform.
  22. //
  23. Void * oalpatova (uint 32 Pa, bool cached)
  24. {
  25. Oal_address_table * ptable = g_oaladdresstable;
  26. Void * Va = NULL;
  27. Oalmsg (oal_memory & oal_func, (L "+ oalpatova (0x % x, % d) \ r \ n", Pa, cached ));
  28. // Search the table for address range
  29. While (ptable-> size! = 0 ){
  30. If (
  31. Pa> = ptable-> PA &&
  32. Pa <= (ptable-> pa + (ptable-> size <20)-1)
  33. ) Break; // match found to find similar memory in the table
  34. Ptable ++;
  35. }
  36. // If address table entry is valid compute the VA
  37. If (ptable-> size! = 0 ){
  38. Va = (void *) (ptable-> Ca + (Pa-ptable-> Pa ));
  39. // If VA is Uncached, set the Uncached bit
  40. If (! Cached) (uint32) va | = oal_memory_cache_bit;
  41. }
  42. // Indicate the virtual address
  43. Oalmsg (oal_memory & oal_func, (L "-oalpatova (Va = 0x % 08x) \ r \ n", VA ));
  44. Return Va;
  45. }
  46. //------------------------------------------------------------------------------
  47. //
  48. // Function: oalvatopa
  49. //
  50. // Converts a virtual address (VA) to a physical address (Pa). This routine
  51. // Uses the oemaddresstable defined in the platform.
  52. //
  53. Uint32 oalvatopa (void * PVA)
  54. {
  55. Oal_address_table * ptable = g_oaladdresstable;
  56. Uint32 Va = (uint32) PVA;
  57. Udint 32 Pa = 0;
  58. Oalmsg (oal_memory & oal_func, (L "+ oalvatopa (0x % 08x) \ r \ n", PVA ));
  59. // Virtual address must be in cached or Uncached regions. Virtual Memory range
  60. If (va <0x80000000 | va> = 0xc0000000 ){
  61. Oalmsg (oal_error ,(
  62. L "error: oalvatopa: Invalid virtual address 0x % 08x \ r \ n", PVA
  63. ));
  64. Goto cleanup;
  65. }
  66. // Address must be cached, as entries in oemaddresstable are cached address.
  67. Va = va &~ Oal_memory_cache_bit;
  68. // Search the table for address range
  69. While (ptable-> size! = 0 ){
  70. If (va> = ptable-> Ca & va <= ptable-> Ca + (ptable-> size <20)-1 ){
  71. Break;
  72. }
  73. Ptable ++;
  74. }
  75. // If address table entry is valid compute the PA
  76. If (ptable-> size! = 0) pA = ptable-> pa + va-ptable-> Ca;
  77. Cleanup:
  78. // Indicate physical address
  79. Oalmsg (oal_memory & oal_func, (L "-oalvatopa (Pa = 0x % x) \ r \ n", PA ));
  80. Return Pa;
  81. }
  82. //------------------------------------------------------------------------------
  83. // From the two functions, we can see that this table is only for ease of modification. In fact, manual access to virtual memory is also possible.
  84. . As for the access to gpio, I will leave it for a moment. Good luck has gained a lot today.

Reprinted Please note: the author wogoyixikexie @ gliet. Guilin University of electronic science and technology, a Department of Science and Technology Association. If any error occurs, you can leave a message to indicate it.

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