How is the oemaddresstable memory ing table used by wince?

1. ;------------------------------------------------------------------------------
2. ;
3. ; File: memory_cfg.inc
4. ;
5. ; This file is used to define g_oaladdresstable. This table is passed
6. ; Kernelstart To estabilish physical to virtual memory mapping. This table
7. ; Is used also in iomem oal module to map between physical and virtual
8. ; Memory addresses via oalpatova/oalvatopa functions.
9. ;
10. ;------------------------------------------------------------------------------
12. ; Export Definition
14. Export g_oaladdresstable [Data]
16. ;------------------------------------------------------------------------------
17. ;
18. ; Table format
19. ; Cached address, physical address, size
20. ;------------------------------------------------------------------------------
22. G_oaladdresstable
24. DCD 0x80000000, 0x30000000, 64; 32 mb dram Bank 6
25. DCD 0x84000000, 0x10000000, 32; ngcs2: PCMCIA/pccard
26. DCD 0x86000000, 0x18000000, 32; 32 MB srom (SRAM/ROM) Bank 3
27. DCD 0x88000000, 0x20000000, 32; 32 MB srom (SRAM/ROM) Bank 4
28. DCD 0x8a000000, 0x28000000, 32; 32 MB srom (SRAM/ROM) Bank 5
29. DCD 0x8c000000, 0x08000000, 32; 32 MB srom (SRAM/ROM) Bank 1
30. DCD 0x90800000, 0x48000000, 1; memory control register
31. DCD 0x90900000, 0x49000000, 1; USB Host register
32. DCD 0x90a00000, 0x4a000000, 1; interrupt control register
33. DCD 0x90b00000, 0x4b000000, 1; DMA control register
34. DCD 0x90c00000, 0x4c000000, 1; clock & Power register
35. DCD 0x90d00000, 0x4d000000, 1; LCD control register
36. DCD 0x90e00000, 0x4e000000, 1; NAND Flash control register
37. DCD 0x90f00000, 0x4f000000, 1; camera control register
38. DCD 0x91000000, 0x50000000, 1; UART control register
39. DCD 0x91100000, 0x51000000, 1; PWM timer register
40. DCD 0x91200000, 0x52000000, 1; USB device register
41. DCD 0x91300000, 0x53000000, 1; watchdog timer register
42. DCD 0x91400000, 0x54000000, 1; IIC control register
43. DCD 0x91500000, 0x55000000, 1; IIS control register
44. DCD 0x91600000, 0x56000000, 1; I/O port register
45. DCD 0x91700000, Zero X 57000000, 1; RTC control register
46. DCD 0x91800000, 0x58000000, 1; A/D convert register
47. DCD 0x91900000, 0x59000000, 1; SPI register
48. DCD 0x91a00000, 0x5a000000, 1; SD interface register
49. DCD 0x92000000, 0x00000000, 32; 32 MB srom (SRAM/ROM) Bank 0
50. DCD 0x00000000, 0x00000000, 0; end of table
52. ;------------------------------------------------------------------------------
54. End

In the past, I never knew what was going on with this table. I had a chance to call his function.

C: \ wince500 \ platform \ common \ SRC \ Arm \ common \ Memory. c

2. //------------------------------------------------------------------------------
3. //
4. // File: memory. c
5. // The code shows the relationship between the arm virtual memory and the physical memory.
6. // Memory interface routines.
7. //
8. # Include <windows. h>
9. # Include <oal_log.h>
10. # Include <oal_memory.h>
12. Typedef struct {
13. Uint32 CA; // cached virtual address
14. Uint32 Pa; // physical address
15. Uint32 size; // size, in MB bytes
16. } Oal_address_table, * poal_address_table;
18. //------------------------------------------------------------------------------
21. //------------------------------------------------------------------------------
22. //
23. // Function: oalpatova
24. //
25. // Converts a physical address (PA) to a virtual address (VA). This routine
26. // Uses the oemaddresstable defined in the platform.
27. //
28. Void * oalpatova (uint 32 Pa, bool cached)
29. {
30. Oal_address_table * ptable = g_oaladdresstable;
31. Void * Va = NULL;
33. Oalmsg (oal_memory & oal_func, (L "+ oalpatova (0x % x, % d) \ r \ n", Pa, cached ));
35. // Search the table for address range
36. While (ptable-> size! = 0 ){
37. If (
38. Pa> = ptable-> PA &&
39. Pa <= (ptable-> pa + (ptable-> size <20)-1)
40. ) Break; // match found to find similar memory in the table
41. Ptable ++;
42. }
44. // If address table entry is valid compute the VA
45. If (ptable-> size! = 0 ){
46. Va = (void *) (ptable-> Ca + (Pa-ptable-> Pa ));
47. // If VA is Uncached, set the Uncached bit
48. If (! Cached) (uint32) va | = oal_memory_cache_bit;
49. }
51. // Indicate the virtual address
52. Oalmsg (oal_memory & oal_func, (L "-oalpatova (Va = 0x % 08x) \ r \ n", VA ));
53. Return Va;
54. }
57. //------------------------------------------------------------------------------
58. //
59. // Function: oalvatopa
60. //
61. // Converts a virtual address (VA) to a physical address (Pa). This routine
62. // Uses the oemaddresstable defined in the platform.
63. //
64. Uint32 oalvatopa (void * PVA)
65. {
66. Oal_address_table * ptable = g_oaladdresstable;
67. Uint32 Va = (uint32) PVA;
68. Udint 32 Pa = 0;
70. Oalmsg (oal_memory & oal_func, (L "+ oalvatopa (0x % 08x) \ r \ n", PVA ));
72. // Virtual address must be in cached or Uncached regions. Virtual Memory range
73. If (va <0x80000000 | va> = 0xc0000000 ){
74. Oalmsg (oal_error ,(
75. L "error: oalvatopa: Invalid virtual address 0x % 08x \ r \ n", PVA
76. ));
77. Goto cleanup;
78. }
80. // Address must be cached, as entries in oemaddresstable are cached address.
81. Va = va &~ Oal_memory_cache_bit;
83. // Search the table for address range
84. While (ptable-> size! = 0 ){
85. If (va> = ptable-> Ca & va <= ptable-> Ca + (ptable-> size <20)-1 ){
86. Break;
87. }
88. Ptable ++;
89. }
91. // If address table entry is valid compute the PA
92. If (ptable-> size! = 0) pA = ptable-> pa + va-ptable-> Ca;
94. Cleanup:
95. // Indicate physical address
96. Oalmsg (oal_memory & oal_func, (L "-oalvatopa (Pa = 0x % x) \ r \ n", PA ));
97. Return Pa;
98. }
100. //------------------------------------------------------------------------------
101. // From the two functions, we can see that this table is only for ease of modification. In fact, manual access to virtual memory is also possible.
102. . As for the access to gpio, I will leave it for a moment. Good luck has gained a lot today.

Reprinted Please note: the author wogoyixikexie @ gliet. Guilin University of electronic science and technology, a Department of Science and Technology Association. If any error occurs, you can leave a message to indicate it.