How Mac and PHY achieve network adaptive

These two days to modify the network card driver to achieve 10/100/1000m adaptive, so the next PHY chip and EMAC driver to the compatibility of 10/100/1000m network environment, recorded here.
Network device-side Data link layer is composed of MAC Chip and PHY chip, PHY chip based on the external network environment to complete the automatic negotiation and configuration, drive in accordance with the PHY state to configure the Mac to achieve PHY and Mac work with each other.
Now the mainstream network card PHY chip for 100M and 1000M, are backward compatible. 100M PHY supports 10/100m environment, 1000M PHY supports 10/100/1000m environment.

First of all, 10/100/1000m refers to the data transceiver rate, the unit is bps. So here's the Mac and PHY data transceiver interface. Mac and PHY mainstream data interface has gmii MII rmii and so on. The interface specification defines the number of data transceiver lines. Interface definitions can read this article:
http://blog.csdn.net/skyflying2012/article/details/8252843

Take Gmii/mii as an example to study, Gmii has 8 rx/tx lines, Mii have 4 rx/tx lines.
First, the 100Mphy chip is studied. PHY completes automatic negotiation with the outside network environment to determine its own speed. 100M PHY supports the Mii interface, so the Mac end needs to be connected to PHY with the Mii interface definition.
The most important thing is to provide the correct data clock to ensure the correct sampling and sending of data.
For 100M PHY, this problem is solved, because the Mii interface supports 10/100m,4 root data line, only need Mac to provide 2.5/25mhz data clock to PHY.

The most worthy research is how to adapt to the 10/100/1000M network environment when external 1000M PHY.
First of all, this is a backward process, first of all see how PHY is dealing with 10/100m and 1000M environment. The Mac interface mode and clock are then configured according to the PHY configuration.
Random Find a 1000M PHY chip datasheet,rtl88e1111, for the Gmii/mii interface description is as follows:

According to this description, GMII interface mode supports the 1000M environment, but in the 10/100m environment after the PHY completes automatic negotiation 10/100base-tx switch to MII mode, Gmii PIN is compatible with MII (Mii under 8 data lines have 4), The GMII interface definition has 2 CLK lines, GTX_CLK tx_clk (gmii/mii under Rx CLK is provided by PHY), GTX_CLK in GMII mode and 125MHZ,TX_CLK in Mii mode. A Mac and 1000M PHY hardware circuit Connection diagram is given below.

Can be seen for 1000M PHY,GTX_CLK TX_CLK all need to connect with the Mac, in the 10/100/1000m environment I used to measure the oscilloscope CLK is indeed said.

in a comprehensive sense,

for 100M PHY, the external network 10/100m switch, only need to change the MAC provides the data clock, the Mac interface mode is unchanged, because Mii compatible 10/100m. for 1000M PHY, external network 10/100/1000m switch, first need to change the Mac interface mode (the number of data lines used is different), because the 10/100m PHY will switch to MII mode, according to the interface mode in changing its data clock.


Of course PHY after the completion of automatic negotiation is its hardware logic will complete the transformation of the mode Gmii/mii, and for the Mac, it should be driven according to the PHY's working state to determine the Mac interface mode and the need to provide CLK.
This is also our software developers most need to pay attention to, according to the PHY status, how to configure the Mac (interface mode data clock) to ensure that the PHY consistent.