How SDRAM works

How SDRAM works

The reason why SDRAM becomes a drarm is that it constantly refresh to retain data. Therefore, it is the most important operation of dram. The time interval between refresh and refresh is usually determined by the fact that the maximum valid storage period of capacitor data in the storage body is 64 ms (millisecond, 1/1000 S ), that is to say, the cycle for refreshing each row is 64 ms. The refresh speed is: the number of rows/64 ms. We often see 4096
Refresh cycles/64ms or 8192 refresh cycles/64ms. Here, 4096 and 8192 represent the number of rows in each bank of the chip. The refresh command is valid for one row at a time. The sending interval also varies with the total number of rows. The 4096 rows are 15.625 μs (microseconds, 1/1000 milliseconds), and The 8192 rows are 7.8125 μs. Hy57v561620 is 8192 refresh cycles/64 ms.

SDRAM is a multi-bank structure. For example, in a module with two banks, one bank can be read immediately during pre-charging, in this way, when the pre-Charged Bank data is read immediately after a read operation, the data can be directly read without waiting, which greatly improves the access speed of the memory.

To implement this function, SDRAM needs to manage multiple banks to control their pre-charging. In an SDRAM with more than two banks, there is usually one more pin called ban, which is used to select between multiple banks.

SDRAM has multiple working modes, and internal operations are a complex state machine. The pins of the SDRAM device are divided into the following categories.

(1) control signal: includes chip selection, clock, clock enabling, row and column address selection, read/write validity, and data validity.

(2) address signal: The time division multiplexing pin selects the pin based on the row and column addresses, and controls the input address as the row address or column address ..

(3) data signal: bidirectional pins, effectively controlled by data.

All the operations of SDRAM are synchronized to the clock. Multiple Input commands can be generated based on the status of the control pin and address on the rising edge of the clock.

Mode register setting command.

Activation command.

Prefill command.

READ command.

Write commands.

READ command with pre-charge.

Write command with prefill.

Auto refresh command.

Self-Refresh command.

Sudden stop command.

Empty Operation Command.

According to the input command, the SDRAM status is transferred between internal states. The internal status includes the mode register setting status, activation status, pre-charge status, write status, read status, pre-charge read status, pre-charge write status, automatic refresh status, and self-Refresh status.

The operation commands supported by SDRAM include Initialization Configuration, pre-charging, line activation, read operations, write operations, automatic refresh, and self-Refresh. All operation commands are input through the control line Cs #, Ras #, CAS #, we #, address line, and body selection address Ba.

　　1. Line Activation

The line activation command selects any row in the idle storage body to enter the ready read/write status. The interval between activating the body and enabling the input of read/write commands depends on the internal feature latency and clock frequency. Hy57v561620 has four internal devices. To reduce the number of device doors, some circuits between the four are public, so they cannot be activated at the same time, in addition, there must be a certain interval between the activation of an individual and the activation of another body.

　　2. Pre-Charging

The pre-charge command is used to pre-charge activated lines to terminate the active status. The pre-charge command can act on a single individual or all bodies at the same time (through the pre-charge command of all bodies ). For the burst write operation, you must ensure that the write operation is completed before writing the Pre-charging command, and use dqm to prohibit Data Writing. After the pre-charging is completed, the system returns to the idle state and can be activated again. You can also enter operation commands such as low power consumption, automatic refresh, auto refresh, and mode setting.

The refresh and refresh operations in pre-charging are the same, except that pre-charging is not performed on a regular basis, but only after reading the operation. Because the read operation will damage the charge in the memory. Therefore, the memory not only needs to be refreshed every 64 ms, but also once after each read operation.

　　3. Automatic pre-Charging

If the location of A10/AP is "1" in the read/write command, a pre-charge action is automatically attached after the read/write operation is completed. The operation line ends the activity state, but a new operation command cannot be sent to the device before the internal state machine returns to the idle state.

　　4. burst read

The burst read command allows an individual row to read several data records after being activated. The first data is displayed on the data line after the specified CAS delay cycle, and a new data will be read at each clock cycle in the future. The burst read operation can be aborted by the new burst read/write commands of the same body or different bodies, or the pre-charging command of the same body and the burst Stop command.

　　5. Burst writing

The burst write command is similar to the burst read command. After an individual row is activated, several data records are continuously written. The first write data and the burst write command are provided on the data line at the same time. A new data is provided for each clock cycle in the future. The input buffer stops receiving data after the burst data volume meets the requirements. The burst write operation can be aborted by the burst read/write command, dqm data input blocking command, pre-charging command, or the burst Stop command.

　　6. Automatic refresh

Due to the leakage of dynamic memory storage units, hy57v561620 must refresh all storage units within 64 ms to ensure data correctness of each storage unit. One automatic refresh cycle can only refresh one row of the storage unit. After each refresh operation, the internal refresh address counter automatically adds "1 ". The automatic refresh operation can be started only when all bodies are idle (because the corresponding rows of the four bodies are refreshed at the same time) and not in low-power mode. During the refresh operation, only null operations can be entered, after the refresh operation is completed, all bodies enter the idle state. The device can execute an automatic refresh command every 7.8 μs, or refresh all units in a period of 64 ms.

　　7. Self-Refresh

Auto-refresh is another way of refreshing dynamic memory. It is usually used to keep the data of SDRAM in low power mode. In auto-Refresh mode, SDRAM disables all internal clock and input buffering (excluding cke ). To reduce power consumption, the refresh address and refresh time are all generated inside the device. Once the auto-Refresh mode is enabled, it can be activated only when the value of cke is reduced. Other input does not work. After the command to exit the auto-Refresh mode is provided, null operation input must be kept at a certain frequency to ensure that the device exits from the auto-Refresh mode. If you use the Centralized Automatic refresh mode during normal operation, you must perform the automatic refresh operation once (8192 for hy57v561620) after you exit the auto-Refresh mode.

　　8. Clock and clock shielding

The clock signal is the synchronous signal for all operations, and the rising edge is valid. The cke of the clock shielding signal determines whether to apply the clock input to an internal circuit. During the read/write operation, the output status and burst address are frozen at the next beat after cke becomes low until cke becomes high. When all the bodies are in idle state, the next beat SDRAM after cke becomes low enters the low power consumption mode and keeps until cke becomes high.

　　9. dqm operations

Dqm is used to block input and output operations. For an output, it is equivalent to an open door signal. For an input, it is prohibited to write data from the total online storage unit. The dqm delay of the read operation starts to take effect for two clock cycles, and the write operation is effective for the timer.