How to determine CS8900 base address

Start to study the implementation method of TFTP. The framework is basically (from the bottom up): media-> ip-> UDP-> TFTP. Cs8900a can complete all the work on the PHY and MAC layers, and there should be a logical link control (LLC) in the upper part of the media. The IP layer not only includes the IP protocol, in addition, the ARP Protocol is required to determine the MAC address of the host. The overall framework is described in detail later. Next we will briefly introduce the method for determining the base address of cs8900a and the probe program.

Cs8900a is actually old, and its performance and price are far lower than dm9000. The default kernel of Linux 2.6 is the Ethernet controller that supports dm9000. But the EDUKIT-III still uses cs8900a, so still focus on cs8900a. Note that the first is to study the learning attitude, and the second is to summarize and read the datasheet method.

First, let's see what cs8900a is.

· Single-Chip IEEE 802.3 Ethernet controller with direct Isa-Bus Interface
· Maximum current consumption = 55 Ma (5 V supply)
· 3 V or 5 V Operation
· Industrial temperature range
· Comprehensive suite of software drivers available
· Efficient packetpage architecture operates in I/O and memory space, and as DMA slave
· Full Duplex Operation
· On-chip RAM buffers transmit and receiveframes
· 10base-T port with analog filters, provides:
-Automatic polarity detection and correction
· AuI port for 10base2, 10base5 and 10base-f
· Programmable transmit features:
-Automatic re-transmission on collision
-Automatic padding and CRC generation
· Programmable receive features:
-Stream Transfer; for reduced CPU overhead
-Auto-switch between DMA and On-chip memory
-Early interrupts for frame pre-processing
-Automatic Rejection of erroneous packets
· EEPROM support for jumperless Configuration
· Boot prom support for diskless Systems
· Boundary scan and loopback test
· LED Drivers for Link Status and LAN Activity
· Standby and suspend sleep modes

We can see that the most important part of cs8900a is:

· ISA bus interface. This part minimizes external glue logic, simplifies programming, and facilitates design.
· Integrate 10base-t transmit and receive filters. With the cables corresponding to the dedicated transformer and RJ45, you can complete the functions of the PHY layer. Therefore, you do not need to consider the PHY chip when designing the hardware. The at91rm9200 is integrated with the Ethernet controller, but only implements the MAC layer function. Therefore, you need to expand a PHY Layer Chip to design the network interface.
· Special packetpage architecture. This is actually a feature of cs8900a. The IO access mode is different from the memory access mode, but cs8900a shields this difference and provides a unified interface. In this way, you can use a unified memory space to complete operations on cs8900a.
· Support for EEPROM.

Now we will analyze the packetpage architecture and the two access modes.

The cs8900a architecture is based on a unique, highly-efficient method of accessing internal registers and buffer memory known as packetpage. packetpage provides a uniied way of controlling the cs8900a in memory or
I/O space that minimizes CPU overhead and simplifies software. It provides a flexible set of performance features and configuration options, allowing designers to develop Ethernet circuits that meet their particle system requirements.

Cs8900a has two access modes: Io mode and MEM mode. In Io mode, cs8900a occupies the smallest space of the host, only 16 bytes (8 16-bit Io ports ). It is a suitable choice for systems with insufficient address space. In mem mode, cs8900a occupies 4 K space, which means that the software can directly access the internal registers of cs8900a, and the 4 K space is also divided into 6 components, for more information, see section 4.1.1 of datasheet.

Cs8900a adopts the IO mode by default. In system design, it is best to reserve both modes. There are many reasons. First, in most cases, the mem mode has higher performance. Because ISA memory operations require less clock cycles than IO operations. Therefore, the mem mode is recommended. Secondly, if the memory space is unavailable or special operations are performed, the IO mode is the only option, and if the EEPROM is used, when the Board fails, the EEPROM is usually blank, to program EEPROM, cs8900a must also work in Io mode. To sum up the two analyses, it is better to design two access methods for the system design. In the ISA bus interface, I/O space and memory space are independently addressable, so they have different read/write signals. However, in the arm system, I/O space and memory space are uniformly addressable. The problem arises. If the two access modes exist at the same time, how can we differentiate the access modes?

This is a common problem in hardware design. During circuit design, addr24 is decoded by the combined logic to distinguish read/write between I/O space and memory space. Cs8900a only needs 20 addresses, and the address line of S3C2410 is 32. Then let a [] correspond to the SA [] of cs8900a and come up with an address line A24 to distinguish the two modes. I drew a schematic diagram (note that this is only one of the combined logic decoding methods. There can be other methods, which are determined by the hardware design), as follows:

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Through the above schematic, it is easy to understand that the A24 address line is in MEM mode when it is low. When the value of A24 is high, the I/O mode is used. In addition, cs8900a can be connected to different banks. For example, if edukit is connected to ngcs3 and the base address is 0x18000000, the base address in MEM mode is 0x18000000, while that in Io mode is 0x18000000 + (1

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