How to improve the timing of FPGA

Eight tips for solving FPGA timing problems

Advice one, if the timing difference is not much, within 1NS, can be modified by the synthesis, layout and routing options to fix, if the difference is much, you have to move the code.

Second, take a look at the timing report, pick a path with the most tight timing, and take a closer look at what the reason is, first look at the number of logical series? What kind of circuit is wrong, the multiplier or the Ram interface data to figure out where the problem first

Advice three, make timing optimization words insert Register is king but also depends on the specific situation does not have to be inserted register, insert register effect is not obvious, first check the position of register INSERT, if register is not in the middle of critical path insert but at one end, really not obvious

Advice four, the key path to find out, see the timing report, see what causes the frequency does not go, if the combination of logic complex, optimization logic or replication logic, if the DSP delay is large, the selection of multi-level water, as long as you want to get 150, it is certain.

Advice five, look at the time series report, it is recommended to look at the same time with the circuit diagram, so the most intuitive

Advice six, the control code, the key path involved in part of the circuit diagram to draw out, and then according to the timing requirements, calculate how many registers to insert, where suitable

Advice seven, 32BIT Comparator, carry chain is a bit long, can be segmented comparison, divided into 4 8BIT data segment to the ratio, or you divided into two segments, the first ratio of 16, insert register, then lower than 16, the timing is very good, if you want to go deeper, on your own handwriting a comparator, do not tune the library.

Advice eight, multi-bit logic, time series not go, usually is the carry chain is too long, usually is to break the carry chain, it is recommended to look at the calculation method or digital algorithm and other books, should be helpful

How to improve the timing of FPGA