How to optimize the FPGA design area (logical resource usage optimization)

When FPGA area optimization 1 does not require high speed, we can design the pipeline into an iterative form to reuse resources with the same FPGA functionality.
2. When the control logic is smaller than the sharing logic, the control logic resources can be used for reuse. For example, in the implementation of the FIR filter, the multiplier is a shared resource. We can implement the state machine by controlling the resources, so as to reuse the multiplier, of course, this also sacrifices the area.
3. For modules with similar counting units, you can use global counters to reduce the area. For example, if module A requires a 256 cyclic count and Module B requires a 1000 cyclic count, we can design a global counter with a counter count of 10 and the first eight digits for module, the entire counter is used by B. A more flexible global counter design can be achieved by rationally using PLL for frequency division.
4. Not all internal logic resources of FPGA support reset (Synchronous Reset, Asynchronous Reset) and set bit. Improper resetting increases resource overhead. For example, a DSP, Ram only supports Synchronous Reset. Reset is not supported for shift registers, and slot is not supported for multiplier.
5. Reset the position to optimize the combination logic. For example, for a | B, we can directly connect a to the input end of the trigger, and B to the position segment of the trigger, this saves one or more resources.
6. Reset and placement should be avoided for circuits with relatively tight area requirements.