How to see the time series diagram--nand Flash read operation detailed

This article is not about the physical structure of NAND flash and some basic knowledge about NAND flash. You need to know at least the physical structure of NAND flash on your hands and some such as read-write commands

The general impression of the operation, you should at least have seen the description of the NAND Flash control register in s3c2440.

As I have not specifically learned this knowledge, the following introduction is also the experience.

here I used it. k9f2g08-scb0 this model NAND Flash to introduce the reading of time series diagrams. Different chip operation timing may be different, read the command will have some differences .

Of course, sometimes like NAND flash this s3c2440 internal integration of his controller peripherals. Detailed timing of the details to the read/write operation (e.g., the settling time of the Cle/ale, the width of the pulse. Data to establish and maintain time, etc.), do not understand the pre-and there is no big problem.

Because the S3C2440 internal NAND flash controller does most of the work, the basic thing you need to do is set a few time parameters. NAND Flash will then perform these details automatically.

Of course, if the processor does not have integrated NAND flash controller So long must write their own timing operation. So it's always good to know the bottom of the sequence.

But the upper level, such as read and write operation of the sequence of steps (such as reading operations, you want to select Enable, then send a command, then send an address, need to send a command, and then need to wait for the operation to complete, and then read the data).

It has to be understood. If this is not understood, how to operate the device?

In other words, s3c2440 can be said that after you set a few time parameters, each step of the minor operations are done for you. (for example, to write a command, you just write a command to the corresponding register, the CPU will be the internal association of the various pins issued

Signal to achieve the operation of the Write command).

All we have to do is write the commands, write the address, and wait for the operation to complete. and other steps together. Thus completing a read operation

As stated above, although we do not need to write the smallest timings in each step. But know the next. will give you a clearer understanding of the underlying details of each procedure.

Let's take a look at the timing of a command latch. That's what it says. There is not a write command step in the read NAND flash operation. So how does this step come true?

First of all, we must choose NAND flash. It's only a chip to make him work.

NAND Flash is through ale/cle ( active High ) to differentiate data on the data line when the command ( CLE valid), address ( ALE valid) or data ( Cle/ale are not valid).

So, since this is a command, then it must be CLE Active (High level) ALE invalid (Low level).

the same order, since it was written NAND Flash the so there must be a write cycle. What we need to note is whether the write is valid on the rising edge or the falling edge .

The timing diagram is as follows:

1 here is the command latch is the timing, then we have to pay attention to the fact that only the CLE is high level during this time series. (Write command Ah, CLE when active (High level) indicates the current data in fact commands) ale at this time must be low we can not care about him

2 So, CLE is a low-level period, and most of the other pins are shaded in shades of gray, which means we don't need to care about the levels of these pins during this period.

3 So when was this data read by NAND Flash, notice that the NWE signal has a vertical line running through all the other pin timings on the rising edge (which seems to be called lifelines?). I don't know, either.

This is the description, the data written (the command is also the data ah, can only be distinguished by CLE Effective) is in We the rising edge of the effective.

in other words, although WE is active at the low level, but not that WE As soon as it becomes low, the command is latched (that is, the command is actually obtained) but WE of the rising edge of the command before it is actually latched .

Know the above three points, also know a probably, then the rest of the figure is only those txx of the label. Obviously it refers to time, but specifically what time it is.

Refers to the time between the two vertical lines indicated by the arrows. (There are small vertical lines at each signal's jump edge)

What's left is what this time represents. There is nothing difficult, just contact with the feeling can not understand. It's because I've never been in touch before. (Just like the MCU just learned when not all kinds of do not understand, the reason is that we have never contacted).
These time labels are described in front of the data sheet.

For example TCLS TCLH from the data sheet we can see the CLE settling time represented by the sub-table, and the CLE signal hold time.

Simple point you can understand that, I let the CLE pin into a high level, must give the world a little time to become high level bar. It can't be turned into a high level in a moment.

However, we can see more clues from the timing diagram, not that we have a vertical line that is longest across other signal lines on the rising edge of we . We say he instructed, the data (the command is also the data)

is locked on the rising edge, on the rising edge of we , I write the command data on the data line to be really latched (received), but we notice that the CLE The signal is valid before we go up the edge.

So we say that theCLE valid TCLS time is called before the command data is really latched. 9> CLE signal settling time.

WE rising edge upon. The command has been accepted, but at this point the CLE can actually become invalid because the command has been acquired.

But he did not end immediately, but tclh time. Then we call this period of time tclh for CLE hold Time .

Then, according to the instructions in the manual, TCS represents the set-up time of the chip selection signal, and the TCH indicates the chip selection signal hold time

TDS represents data settling time, TDH represents data hold Time

Here we see a small pattern, the time in the data sheet that ends with S usually refers to the settling time, and the time at the end of H refers to the hold time.

The order of the latches here is analyzed. Let's take a look at the address latch timing diagram, which is a bit complicated,

Because the feature of NAND Flash is that the address cycle usually requires several, that is, an address is sent in several times

Give a description of the corresponding time label in the data sheet.

Likewise, we follow the steps in the above analysis

1 here is the address latch is the timing, then we have to pay attention to the fact that only the ALE is high level during this time series. (Write command Ah, ale active (High level) indicates that the current data is actually an address) CLE at this time must be low, you can do without tube

2 So, the ALE is a low-level period, and most of the other pins are shaded in shades of gray, which means we don't need to care about the levels of these pins during this period.

3 likewise WE rise along a long vertical line that runs through other signal lines, which is also representative of the data (here is actually the address) on the rising edge is latched

Then the rest is understandable.

TCLS This we do not need to care, because CLE is ineffective.

TCS, as previously analyzed, refers to the time at which the CE chip selection signal is valid before the We rising edge, which is the latch address, which is the CE settling time

Where's TWC? I don't know? Do not know to read the manual Ah, the previous said that these time labels will be given in the manual.

From the interpretation of the above manual we see that it refers to the time of a write cycle

TWP write pulse width (i.e. we are low level, TWP refers to low level duration, is the effective time)

TWH good understanding, is the high-power normal room

ALS that's not the address signal ALE settling time

ALH Ale Signal to hold the time effectively.

TDS TDH Data setup and retention time

just like the above the analysis of command timing, here Signal of Establish and hold time are the data is latched to the boundary point (WE rising edge )

See here believe that carefully look at the people, should be roughly how to look at a time series diagram, but here we are all involved in some of the above to establish/hold the times.

Complex point of it.

The following is a complex point of the timing diagram, in fact, is not complicated, mainly to explain how to read the manual can know txx refers to what time

This timing is not really complicated, but he is not the same as the above analysis of the set-up time and hold time. It involves a lot of time marking.

But like I said before. Look at the Handbook! Each time parameter is described in the manual. But beginners usually even look at the manual, these time parameters are also not know what the meaning.

Here we look at the manual, the first to analyze it yourself. The way it is, the manual becomes the proof that you are wrong, not what you are looking for.

The TRC parameter is a bit simple. Look at his range is the time of the re cycle, then it should be the same as the previous TWC. It should represent a cycle time of the re signal (a cycle of reading the signal).

TREA it? Look at the label can not see why, then we see his start and end time from the sequence diagram to see, this refers to from the RE Effective (lower) to the data appear The time between.

Then Trea should be the time to read the signal effectively until the data is read.

That's the same analytical method that's behind it.

For example, the last Trhz is the time between the invalid (high level) of the RE and the high impedance of the data line (the data line is represented by the high impedance state in the middle)

Look at the explanations in the handbook, that's basically what it means.

I believe we should be able to understand the timing diagram here. Even if you don't have to read the manual, you know what he means. Because we can infer the meaning of the time label from the starting address of the time.

The above analysis, are very low-level operations, if we use s3c2440 this advanced processor these sequential operations we do not need to implement, at most, we will go to several registers

Set some of the time mentioned above then, the NAND flash controller in the CPU will automatically complete all of the above operations. But the reason you need to know is that if you run into a

NAND Flash Controller's processor what to do, then you can only implement these specific commands, write the address. And so on unit operation.

You can then combine these unit operations into data, write data, and so on (as mentioned above, such as read operations He is not a simple command but a series of operations, you want to select Enable, then send commands (Read command),

Then send the address (the address of the data to be read), need to send a command, and then need to wait for the operation to complete, and then read the data)

Having said these specific unit operations, let's take a look at what steps are required for a read operation. Which is what we really need to know about sequential operations.

For my NAND flash read operation timing is as follows

The main thing to note is that the bottom line is the state of the I/OX signal line, and he indicates what the read operation requires, the unit step.

1 First we see that there is an 0x00 what is it? Data? Address? Command? See ale/cle Line Ah, these two lines are not the type that determines the current data

Looking up, we know that 0x00 is the data during the CLE period. So it's a command.

2 then the address (5Cycle) is the five sequence of addresses (this NAND flash to specify the address of the read data to send five address sequences), looking up, is the ale valid period of data, then should be the address

(for these five addresses, the first two are the column addresses, and the next three are the row addresses.) A page that corresponds to a row address in the physical structure of the NAND flash, and the column address corresponds to a column in the page)

3 Then again 0x30, at this time CLE effective, then is the command (that is, this NAND flash read operation requires two commands).

But then the data didn't come out at once, and we saw that there was a period of time before the data output----------why was it?

Look up r/nb This data line explains why, during this time it is low indicating that it is now busy and not ready for data output. Why is that?

Because you wrote a command, wrote the address to read the data, and wrote a command. You have to give the CPU some time to deal with these commands,

R/NB This is a low-level period. in the process of processing these commands (in effect, the page data you locate is read into the internal register),

when the r/nb becomes high, it indicates that the command has been processed, and now the data can be read out .

We've learned from the manual that we know the exact steps of the read operation,

1 First NAND Flash is also a peripheral, to access it requires a piece of it, so before performing the steps on the sequence diagram requires the chip selected NAND flash.

2 look at the back is the installation sequence diagram, see time series Diagram! The first step is to send a command 0x00.

3 See time series Diagram! Then send five address sequence (send two column address first, send three line address (i.e. page address))

4 See time series Diagram! Then there was a command 0x30.

5 See time series Diagram! R/NB Pin Low indicates that the command is now busy and is being processed, waiting for the R/NB pin to become high

6 See time series Diagram! It's time to read the data.

71 reads the end of the NAND flash is not required to use, then do not forget to cancel the chip selection signal.

As for the specific timing in each of these steps, the NAND Flash controller in the CPU will help us do that. All we have to do is set a few time parameters

Here we have repeatedly stressed the need to look at the timing diagram. In fact, learn the embedded pre-data manual must see more, see more you will know, what things you focus to see, what is unrelated to your programming operation you do not need to care. Then you can get a peripheral to write his operation. Instead of following the back steps. As long as the handbook is on the line.

The above step is a specific read operation, but we need to initialize it before using a device. As far as initialization is set, we have mentioned more than once

We said s3c2440 has helped me do a lot of low-level unit operations, we just need to set a few time parameters on-chip NAND flash will automatically emit the corresponding operation of the timing operation

So what time does it set?

Several parameters that need to be set are given in the s3c2440 manual.

From this we can see that the first sequence diagram is the sequence of command and address latches, and the second is the timing of data read and write.
As you can see, the time they set is the same. Before analyzing so much, it should not be difficult to see

1 Tacls is very clear that is the cle/ale of the establishment time (here is not accurate, in fact, cle/ale effective to we into a low level between the time, but we are on the rising edge of the lock command/address)

2 TWRPH0 represents the pulse width of WE, that is, the effective time

3 TWRPH1 represents the holding time of Cle/ale.

What kind of numbers are they set? Since the time parameters required for the read/write/command/address operation are the same

So let's just get a command sequence from NAND flash.

Take the command latch sequence we talked about above.

then we can get the following relationship.

TWRPH0 = TWP

TWRPH1 = TCLH

tacls = Tcls-twp

And how much is it set? Look at the manual, the manual for TWP TCLH TCLS will give at least the minimum time required

These three parameter requirements in this chip NAND flash manual are

So TWRPH0 = TWP >=12ns

TWRPH1 = TCLH >=5ns

Tacls = Tcls-twp >=0;

And these three parameters are described in the s3c2440 data sheet as

Of course, the time here is in HCLK, these parameters are set in the NAND Flash control register in the nfconf

I don't use MPLL here, so HCLK is 12MHZ.

So TWRPH0 = 0 TWRPH1 =0 tacls = 0; (If you have a high clock frequency, you need to set a different number.) Of course there are you really do not know, set the big point is always right, but the speed may be slow. )

So nfconf =0; (nofconf other bits in the data sheet, this is just a simple read operation, other bits can not be set)

Then initialize the ECC enable NAND Flash Controller (we just set a few time parameters, the specific operation of the timing is done by him, so to enable him)

Then remove the chip-select NAND Flash first because we haven't manipulated it yet, just initialize it. So we should cancel the chip selection first, and so on when the real reading to enable the chip to select the signal

Nfcont = (1<<4) | (1<<1) (1<<0);

(Description of the corresponding bit in the data sheet)

Finally, for the first time using NAND flash we need to reset the operation.

In summary, the initialization code for NAND Flash is as follows

void Nand_init (void) {

nfconf = 0;

Nfcont = (1<<4) | (1<<1) | (1<<0);

Nand_reset (); NAND reset code in the back

}

Some of the following code addresses are written in relation to NAND flash models. Reference chip manuals for specific needs

void Select_chip (void) {

Nfcont &= (~ (1<<1));

int i;

for (i=10;i>0;i--);

}

void Deselect_chip (void) {

Nfcont |= (1<<1);

int i;

for (i=10;i>0;i--);

}

void Write_command (unsigned char command) {

NFCMMD = command;

int i;

for (i=10;i>0;i--);

}

/*

This NAND flash page size is 2K

Five address cycles (2 column address and 3 and Line address (page address))

*/

void write_address (unsigned int address) {

unsigned int page = address/2048;

unsigned int col = address&2048;

int i;

nfaddr = col & 0xFF;

for (i=5;i>0;i--);

Nfaddr = (col >>8) & 0x0f;

for (i=5;i>0;i--);

nfaddr = page & 0xFF;

for (i=5;i>0;i--);

nfaddr = (page >>8) & 0xFF;

for (i=5;i>0;i--);

nfaddr = (page >>16) &0x01;

for (i=5;i>0;i--);

}

unsigned char read_one_data (void) {

return nfdata;

int i;

for (i=10;i>0;i--);

}

void Wait_ready (void) {

while (!) ( Nfstat & 1));

int i;

for (i=10;i>0;i--);

}

static void Nand_reset (void) {

Select_chip ();

Write_command (0xFF);

Wait_ready ();

Deselect_chip ();

}

void Nand_init (void) {

nfconf = 0;

Nfcont = (1<<4) | (1<<1) | (1<<0);

Nand_reset ();

}

/*

The read operation for NAND Flash is in pages.

Des:nand where to put the data read in Flash

START_ADDR: Where to start reading

Size: Read how big

*/

void Nand_read (unsigned char *des,unsigned int start_addr,unsigned int size) {

unsigned int col = start_addr & 2048;

Select_chip ();

unsigned int start = START_ADDR;

unsigned int end = start_addr + size;

while (Start < end) {//read a page each time you need to send a command

Write_command (0x00);

Write_address (start);

Write_command (0x30);

Wait_ready ();

while ((col<2048) && (start<end)) {//Read on one page, I use the Model one page size of 2K

*des = Read_one_data ();

des++;

col++;

start++;

}

col = 0;

}

Deselect_chip ();

}

How to see the time series diagram--nand Flash read operation detailed (GO)