I2C is a serial data communication protocol invented by Philips. It only uses two signal lines: serialclock (SCL) and serialdata (SDA ). I2C is a bus structure, with one master, one or more slave. Each slave device is differentiated by a 7-bit address, followed by a read/write bit, indicating read (= 1) or write (= 0), so sometimes we can also see eight-bit device addresses. At this time, each device has two read and write addresses, and the high seven addresses are actually the same. The I2C data format is as follows:
No data: SCL = 1, SDA = 1;
Start: SDA changes from 1 to 0 when the SCL is 1;
Stop: SDA changes from 0 to 1 when the SCL is 1;
Data bit: When the SCL changes from 0 to 1, the sender controls the SDA. In this case, the SDA is valid data and cannot be changed at will;
The data on SDA can be changed at will when the check mark is set to 0;
Address bit: defines the same data bit, but only sends it to slave by the master;
Ack: When the sender sends 8 bits, the sender releases the SDA, which is controlled by the receiver and SDA = 0;
No response bit (NACK): When the sender sends 8 bits, the sender releases SDA, which is controlled by the receiver and SDA = 1. When the data is transmitted in a single byte, the format is:
Start bit, 8-bit address bit (including 1-bit read/write bit), response, 8-bit data, response, stop bit.
When data is transmitted as a string of bytes, the format is:
Start bit, 8-bit address bit (including 1-bit read/write bit), response, 8-bit data, response, 8-bit data, response ,......, 8-bit data, response, and stop bit. Note that:
1. The SCL is always controlled by the master. The SDA is controlled by the slave during data reading and the SDA is controlled by the master during data writing. After the eight-bit data is transferred, the SDA control of the response bit or no response bit is opposite to that of the Data bit transfer.
2. The start bit "start" and stop bit "stop" can only be issued by the master.
3. After the 8-bit address is transferred, the slave device with the address configured must send "Ack ". Otherwise, after a certain period of time, the master will be deemed as time-out, and data transmission will be abandoned and "stop" will be sent ".
4. When writing data, the master sends 8 data bits each time. If the slave device still has space to accept the next byte, it should answer "Ack ", if the slave device does not have space to accept more bytes, it should answer "Nack". When the master receives "Nack" or does not receive any data after a certain period of time, it will be deemed as timeout. At this time, the master abandons data transmission, send "stop ".
5. When reading data, the slave device sends 8 data bits each time. If the master wants to continue reading the next byte, the master should answer "Ack" to prompt the slave to prepare the next data, if the master does not want to read more bytes, the master should answer "Nack" to prompt the slave device to receive the stop signal.
6. When the master node is too fast and the slave end is too late to process the data, the slave device can lower the SCL (the "line and" will occur when the SCL = 0) to prevent the master node from sending more data. In this case, the master will slow down or stop data transmission as needed. In actual application, it is not mandatory that the data receiver must respond to the eight-bit data sent, especially when both the master and slave are implemented using the gpio software simulation method, the programmer can specify the Data Transfer Length in advance, and the slave does not check nack, sometimes it can reduce system overhead. However, if the slave side is a hardware I2C requirement, it must be a standard nack. The master side is a gpio software that simulates I2C and does not correctly send nack, the following error occurs: "slave cannot receive stop", resulting in I2C failure.
