How to use Makefile to compile programs under UNIX

Makefile is related to the compilation rules of the whole project. The source files in a project do not count, by type,

Features, modules are placed in several directories, makefile defines a set of rules to specify which files need to be compiled first, which files need to be compiled, which files need to be recompiled, and even more complex functional operations, because makefile is like a shell script, You can also execute the operating system commands.

The benefit of makefile is that "automated compilation", once written, requires only a make command, the whole

The project is fully automatic compiling, which greatly improves the efficiency of software development. Make is a command tool, a command tool that interprets instructions in makefile.

Compiling principle

In general, whether C, C + +, or PAS, the first to compile the source file into intermediate code files, under Windows is the. obj file, Unix is an. o file, that is, Object file, this action is called compilation (compile). Then a lot of object file is synthesized to execute the file, this action is called link.

At compile time, the compiler needs the correct syntax, the declaration of functions and variables. For the latter, it is usually the location where you need to tell the compiler header file, as long as all the syntax is correct, the compiler can compile the intermediate target file. In general, each source file should correspond to an intermediate target file (o file or obj file).

Links are mainly linked functions and global variables, so we can use these intermediate target files (o files or obj files) to link our applications. The linker does not care about the source file where the function resides, just the intermediate object file of the function, most of the time, because there are too many source files, there are too many intermediate target files generated by the compilation, and when the link needs to clearly indicate the intermediate target filename, which is inconvenient for compiling, We're going to pack the middle target file, which is called the "library file" (libraryfile) in Windows, the. lib file, under UNIX, archive file, or. A.

To sum up, the source file first generates an intermediate target file, which is then generated by the intermediate target file. At compile time, the compiler detects only the program syntax, and whether the function or variable is declared. If the function is not declared, the compiler gives a warning, but can generate object File. And when you link a program, the linker will find the function in all objectfile, if cannot find, that will report link error code (Linker error), in VC, this kind of error is generally: Link 2001 error, meaning say, linker failed to find the implementation of function. You need to specify the object File for the function.

Makefile Introduction

When the make command executes, a Makefile file is required to tell the make command how to compile and

Link programs.

Writing rules:

1 if the project has not been compiled, then all of our C files will be compiled and linked.

2 If some C files of this project are modified, we only compile the modified C file and link

The target program.

3 If the header file of this project has been changed, we need to compile the C file that references these header files.

and link the target program.

Makefile Rules:

Target ...: Prerequisites ...

Command

...

Target is either an object file, or it can be an executable file. It can also be a standard

Sign (label), for the label of this feature, in the subsequent "Pseudo target" section will be described.

Prerequisites is the file or target that is needed to generate the target.

command is what you need to execute. (Arbitrary shell commands)

This is a file dependency, that is, target this or multiple destination files depend on the

A file in prerequisites whose build rule is defined in the command. The white point is that if more than one file in prerequisites is newer than the target file, the commands defined by the command are executed.

This is the makefile rule. Which is the core content of makefile.

Example:

# Link:

EDIT:MAIN.O KBD.O COMMAND.O display.o

Cc-o edit MAIN.O kbd.o command.o display.o

#compile MAIN.O

MAIN.O:MAIN.C Defs.h

Cc-c MAIN.C

#compile KBD.O

KBD.O:KBD.C Defs.h Command.h

Cc-c KBD.C

#compile COMMAND.O

COMMAND.O:COMMAND.C Defs.h Command.h

Cc-c COMMAND.C

#compile DISPLAY.O

DISPLAY.O:DISPLAY.C Defs.h Buffer.h

Cc-c display.c

# Clean:make Clean

Clean:

RM Edit MAIN.O KBD.O COMMAND.O display.o