How to use the 74ls595 (8-bit output latch shift register)

How to use the 74ls595 (8-bit output latch shift register)
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The use of single-chip microcomputer and 74ls595 (8-bit output latch shift register)

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74595 Data End:
QA--QH: Eight-bit parallel output, can directly control the 8 segments of the digital tube.
QH ': cascaded output. I'm going to take it down to a 595 si end.
SI: Serial data input terminal.


Description of the control side of 74595:
/SCLR (10 feet): Low point will normally clear the shift register data. I usually connect it to VCC.
SCK (11 feet): Data shift of data registers on rising edge. qa-->qb-->qc-->...-->qh; falling along the shift register data unchanged. (Pulse width: 5V, more than dozens of nanoseconds on the line.) I usually choose the microsecond level)
RCK (12 feet): When the shift register data enters the data store register when the rising edge, the storage register data is not changed when the falling edge. Usually I set the Rck low, and when the shift is over, a positive pulse (5V, greater than dozens of nanoseconds) is generated at the Rck end. I usually select the microsecond level) and update the display data.
/g (13 feet): Disables the output (high-impedance state) at normal times. If the microcontroller pin is not tense, with a pin control it, you can easily produce flicker and extinction effect. Saves time and effort over data-end shift control.


Note:
1) 74164 and 74595 functions are similar, are 8-bit serial input to parallel output shift register. The 74164 Drive current (25mA) is smaller than the 74595 (35mA), 14-pin package, and smaller in size.
2) The main advantage of 74595 is that it has a data storage register, and the output data can remain unchanged during the shift. This is useful when the serial speed is slow, the digital tube does not have the flicker sense.
3) 595 is a serial into and out with a latch function shift register, its use is very simple, in normal use SCLR is high, g is low level. Each input data from SER, serial 595 is to string in and out with a latch function shift register, it is very simple to use, such as the following truth table, in the normal use of SCLR high level, G is low level. Each input data from SER, the serial input clock sck the rising edge one time, until the eight-bit data input is completed, the output clock rising edge is valid once, at this time, the input data is sent to the output side. Into the clock sck the rising edge is valid once, until the eight-bit data input is completed, the output clock rising edge is valid once, at this time, the input data is sent to the output side.

DS: Serial data input, connected to a digital I/O pin of the Arduino.
The Q0~q7:8-bit parallel data output allows direct control of 8 LEDs, or 8 pins for seven-segment digital tubes.
q7′: Cascade output, connected to the next 74hc595 DS, enables cascade between multiple chips.
74hc595 with control-related pins a total of four:
SH_CP: The clock input of the shift register. On the rising edge, the data in the shift register moves one bit, that is, the data in the Q0 is moved to Q1, the data in the Q1 is moved to Q2, and so on, and the data in the shift register remains the same when the falling edge.
ST_CP: The clock input of the storage register. The data in the shift register enters the storage register when the rising edge, and the data in the storage register remains the same when the falling edge. When applied, the ST_CP is usually set to a low point level, and a positive pulse is generated at the ST_CP end to update the display data at the end of the shift.
MR: Reset resets the data in the shift register to zero at low levels, typically connecting it directly to high level (VCC) when applied.
OE: Output allows, high-voltage prohibit output (low-impedance state). When the pin is not tense, it can be controlled with one of the Arduino pins, which makes it easy to blink and extinguish. The actual application can be directly connected to low level (GND).
For one of the simplest 74hc595 applications, the three digital I/O ports of the Arduino can be used to control the DS, SH_CP, and ST_CP, respectively, and then the MR and OE are respectively connected to VCC and ground.
In fact, read so many 595 of the information, feel no difficulty, the key is to understand its timing diagram, in the final analysis, is the following three steps (citation):


First step: Objective: To move the bit data to be prepared for input into the 74hc595 data input.
Method: Send bit data to P1.0.


The second step: The purpose: To shift the bit data into 74hc595, that is, data string into
Method: P1.2 produces a rising edge and moves the data on the P1.0 into the 74hc595. from low to high.


Step three: Aim: output data in parallel. That is, the data and
Method: P1.1 produces a rising edge that will be moved by the data in the data register on the P1.0
Fed into the output latch.


Description: From the above can be analyzed: from the P1.2 to produce a rising edge (moving into the data) and P1.1 to produce a rising edge
(output data) is two independent processes that are not interfered with in practical applications. Can output the data
The data is also moved in.


and the specific programming method is


such as: R0 storage 3fh,led Digital tube display "0"


; * * * Interface definition:
ds_595 EQU P1.0; serial data input (595-14)
ch_595 EQU P1.2; shift clock pulse (595-11)
ct_595 EQU P1.1; output latch control pulse (595-12)


* * * * * The data in the shift register is latched to the output register and displayed
out_595:
Call wr_595; calls the shift register to receive a byte of data subroutine
CLR ct_595; pull-down latch control pulses
NOP
NOP
Setb ct_595; The rising edge sends the data to the output latch, LED digital tube display "0"
NOP
NOP
CLR ct_595
Ret


* * * * * * shift register receives a byte (such as 3FH) data sub-Program
wr_595:
MOV R4, #08H; one byte of data (8 bits)
MOV a,r0; Store the data to be fed into the R0 3FH
LOOP:
; First step: Prepare to move into 74hc595 data
RLC A; Data shift
MOV ds_595,c; Send data to serial data input (P1.0)
Step two: Generate a rising edge to move data into 74hc595
CLR ch_595; pull low shift clock
NOP
NOP
SETB ch_595; shift on rising edge (move into a data)


DJNZ R4,loop; A byte of data is not finished moving on.
Ret


and its cascade application
74hc595 is mainly applied to dot matrix screen, take 16*16 lattice as an example: transfer a line of two bytes (16 bits)
For example: 06H and 3FH are sent. The method is:
1. Send data 3FH First, then send 06H.
2. After cascade serial input, 3FH in IC2, 06H inside IC1. Application as shown in Figure II
3. Then send the latch clock, the data is latched and appears on the parallel output port of IC1 and IC2.




Programming Methods:
Data in 30H and 31H
; MOV 30H, #3FH
; MOV 31H, #06H


; * * * Interface definition:
ds_595 EQU P1.0; serial data input (595-14)
ch_595 EQU P1.2; shift clock pulse (595-11)
ct_595 EQU P1.1; output latch control pulse (595-12)


* * * * * Serial input 16-bit data
MOV r0,30h
Call wr_595; serial input 3FH
Nop
NOP
MOV r0,31h
Call wr_595; serial input 06H
NOP
NOP
Setb ct_595; The rising edge sends the data to the output latch, showing
NOP
NOP
CLR ct_595
Ret