How to write the state machine in OpenGL

The state machine is the universal key of the time series circuit. All time series circuits can be implemented through the state machine. In the past, I used to write a program using a conventional state machine. Currently, it is popular to use a three-stage state machine. It seems that three paragraphs do not have many advantages.

There are few registers in the CPLD, and the individual feels that it is also possible to use a paragraph, mainly saving resources.

The state of a time series circuit is a collection of state variables. The values of these state variables at any time contain all historical information that must be considered to determine the future behavior of the circuit.

The state machine is encoded using the VerilogHDL language. It is recommended that the state machine be divided into three always segments.

When a three-stage modeling describes the output of the FSM state machine, you only need to specify the case sensitive table as the sub-State Register, and then directly describe the output of this state in the case branch of each sub-state, you do not need to consider the status transfer condition.

Although the Code structure is complicated, the advantage of the three-stage description method is that FSM achieves synchronous register output, eliminating the instability and Glitch of the combined logical output, in addition, it is more conducive to Time Series path grouping. Generally, it has better integrated and layout wiring effects on FPGA/CPLD and other programmable logic devices.

The columns are as follows:

 

// The first process synchronizes the time series always module and formats the description sub-State Register to the current State Register

Always @ (posedge CLK or negedge rst_n) // async Reset

If (! Rst_n)

Current_state <= idle;

Else

Current_state <= next_state; // note that a non-blocking value is used.

 

// The second process, which combines the logic always module to describe the state transfer condition judgment

Always @ (current_state) // Level Trigger

Begin

Next_state = x; // the state to be initialized so that the system enters the correct State After resetting.

Case (current_state)

S1: If (...)

Next_state = S2; // blocking value assignment

...

Endcase

End

 

// The third process synchronizes the time series always module and formats the output of the description sub-State Register.

Always @ (posedge CLK or negedge rst_n)

... // Initialization

Case (next_state)

S1:

Out1 <= 1'b1; // note the non-blocking Logic

S2:

Out2 <= 1' B1;

Default:... // The role of default is to eliminate the need for comprehensive tools to integrate the lock.

Endcase

End

How to write the state machine in OpenGL