How u-boot for mini6410 automatically recognizes memory size

Yesterday we completed the mini6410 U-boot automatic identification of 128 MB and mb ddr memory. Here we record the principles.

1. Understand the principles of DDR SDRAM

First, you must understand the principles and external interfaces of ddr sdram.

Here are some classic articles on the Internet:

Expert explanation: Memory working principle and development history

Memory principle and timing (SDRAM, DDR, DDR-ⅱ, Rambus DRAM)

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2. Relationship between memory hardware structure and addressing of mini6410

After reading the above documents, I believe we should have a complete understanding and understanding of the DDR memory. Let's talk about the memory hardware structure on mini6410:

For the mini6410 design, two pin-compatible DDR memory chips are used to achieve MB memory and MB memory sharing a PCB.

MB memory uses two pieces of k4x201763pg (32mx16bit) to form32m × 32bit (128 MB)
Memory.

MB memory uses two k4x1g163pe (64mx16bit) to form64 MB × 32bit (256 MB)
Memory.

WhileThe difference between the two chips is that the F7 of k4x201763pg is the NC pin, while the F7 pin of k4x1g163pe is A13.

.

This F7 pin is on
In the mini6410 of the mb memory version, this pin is not connected, and in the MB version, it is connected to the xm1addr13 of the euro resistance.

.

Read the twoData Manual for memory chips and cloud6410 (DRAM controller)
You must know that this connection forms an addressing relationship like this:

MB memory version:Xm1addr [15: 14] (bank): xm1addr [12

: 0] (row address): xm1addr [] (column address)
. A total of 25 address lines can address 32 m Space

MB memory version:Xm1addr [15: 14] (bank): xm1addr [13

: 0] (row address): xm1addr [] (column address)
. A total of 26 address lines can address 64 m Space

WhileThese two types of connections and chip configurations must also be matched by modifying the parameters of the two registers of the DRAM controller.

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3. Position of Adaptive Memory code in U-boot

After preparing the above two knowledge items, let's take a look at the locations in U-boot to identify and adapt to different memory sizes.

First
After recognizing the memory size, we may need to reconfigure the memory controller of. In this way, the Code cannot be run in DDR. Because once the memory controller is reconfigured
The memory is temporarily unavailable. If the code is in the DDR, the CPU may not be able to get the next code. Therefore, the code should be placed in the place where u-boot implements the self-copy to the memory, in fact, the best place is
Initialize the code segment of the memory controller in the SPL section of U-boot.

These codes are:ARCH/ARM/CPU/arm1176/cloud64xx/cpu_init.s

This
Files are assembly code, and the mem_ctrl_asm_init function is
In lowlevel_init "------>/board/Samsung/mini6410/lowlevel_init.s
Lowlevel_init "BL
Mem_ctrl_asm_init. The code in the mem_ctrl_asm_init function initializes the DRAM controller of and
The DDR memory is also initialized, so the memory recognition and adaptive code should be placed after the initialization. First, identify the memory size. If the memory size does not match the original DRAM controller configuration
Modify the DRAM controller configuration.

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4. Memory size Recognition

For mini6410, we only need to identify whether the memory is 256 MB or MB. The two memory sizes are related to the parameters of the two registers of the DRAM controller.
We must first assume the memory size, and then prove it through the read/write method. If we prove that our assumptions are incorrect, then modify the register parameters.

In the transplanted U-boot code, we first assume that the memory is 256 MB, and first configure the DRAM controller as the parameter of MB memory.If the connection is MB
So there will be an interesting phenomenon:

Because xm1addr [13

]
No connection, so the first 8m x 32bit (32 MB) of the DDR memory and the second 8m x 32bit (32 MB) are mirror relationships, the third 8m x 32bit (32 MB) and
The fourth 8 Mb × 32bit (32 MB) is the image relationship, and so on. There are a total of four such image relationships, totaling 256 MB. If the connected memory is MB, this will not happen.
Image. Therefore, as long as we prove the existence of this phenomenon, it proves that we are actually connected to the MB memory, and then reconfigure the DRAM controller to set the parameter to MB memory.

Therefore, I first write a 32bitTest Data
To the first 8 Mb x 32 bit (32 MB)A location

(Ratio
For example, 0x0 address), and then read the second 8 Mb × 32 bit (32 MB) offset. If the data is consistent, the image relationship can be proved. But it is not safe.
In the case of MB memory) The second 8 Mb × 32 bit (32 MB) location itself is the data. What should I do? It doesn't matter. Let's go to the second 8 Mb x 32 bit (32 MB)Same location

WriteAnother test data
Then, read the data at the first 8 Mb x 32 bit (32 MB) location (that is, the write location at the beginning). If the data is consistent, the image relationship can be completely proved. Through these two tests, you can see if you want to reconfigure the DRAM controller parameters.

But weNo
Assume that the memory is 128 MB.
And configure the DRAM controller as the parameter of MB memory. If the connection is MB memory, no special phenomenon can be tested. Through the addressing relationship above, if the connection is MB memory, only the second, fourth, sixth, and eighth (assuming xm1addr [13

] Always 0
) 8 Mb × 32 bit (32 MB) is inaccessible (it can be said that it is a memory hole), this cannot pass the read/write proof. (Inferred by addressing relationship, not proved by experiment)

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5. reconfigure the Memory Controller

If the image exists in the above steps, we must reconfigure the values of the two registers, but how to reconfigure it is not described in this Samsung Data Manual, I tested and found that the DRAM controller can be reconfigured through the following steps:

1. Set the DRAM controller to the paused status;

2. Check p1memstat until the paused status is confirmed;

3. Set the DRAM controller to the config status;

4. Check p1memstat until the configuration status is confirmed;

5. Modify the register to be reconfigured

6. Set the DRAM controller to the Go status;

7. Check p1memstat until the ready status is confirmed;

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