I2C bus-based electro-mechanical memory fm31256 with watchdog and real-time clock

AbstractFm31256 is a multi-functional storage chip based on I2C bus and powered by the iron and electronics technology. In addition to non-volatile memory, the device also provides real-time clock, low-voltage reset, watchdog counters, non-volatile event counters, lockable serial digital identification, and other features. This article mainly introduces the basic functions and principles of fm31256, and gives the specific application methods of fm31256 in the electromagnetic casting and rolling power control device based on examples.

KeywordsI2C bus iron and Electronics Technology RTC RJF
Fm31256 is a new generation of multi-function system monitoring and non-volatile ferroic storage chip launched by ramtron. Compared with other non-volatile memory, it has the following advantages:
Fast read/write speed, no write wait time; low power consumption, low static current of less than 1 mA, write current of less than 150mA; long erase life, 10 billion chip writes, it is 0.1 million times higher than general EEPROM Memory, and can be used for 10 years even if the number of reads/writes per second is 30. The read/write is unlimited, and the number of chip writes exceeds 10 billion, it can also read/write data like SRAM.
The core technology of fram is iron transistor materials. This special material provides both a random access memory (RAM) and non-volatile storage. This article introduces the main functions of fm31256 and provides a memory read/write Program Based on Embedded C language.
1 basic structure and principle of fm31256
Fm31256 consists of a 256 kb memory and Processor Companion. Unlike storing data using backup batteries, fm31256 is a real truly nonvolatile memory, and you can choose to write protection for different storage areas in software mode.

The fm31256 device combines non-volatile fram with real-time clock (RTC), processor monitor, non-volatile event counter, programmable lockable 64-bit ID and universal comparator. Among them, the general purpose comparator can play a role in advance when the power supply is interrupted (NMI) or for other purposes. Using an advanced 0.35 μm manufacturing process, these features are embedded into 14-pin soic packages through a common interface to replace multiple components on the system board. Memory read/write and other control functions are implemented through the Industrial Standard I2C bus.

Figure 1 shows the schematic of fm31256. The SDA and SCL pins are used for data exchange and command writing with the CPU. The data output has Schmidt triggers to improve anti-interference performance. At the same time, SDA serves as a bidirectional signal line in the second-line interface, open collector output, which can be connected to other devices on the second-line bus ". A1 ~ A0 selects a signal for the device address, that is, four similar devices can be used simultaneously on the bus. In normal mode, the PFI pins are the comparator input (not left blank), the cal/PFO pins output the PFI pin input signal and the comparison result between the 1.2v reference voltage; in calibration mode, the cal/PFO pin outputs a 512Hz square wave for clock calibration. Cnt2 ~ Cnt1 is the two-way input end of the event counter supported by the backup battery. It is triggered by the edge and the trigger edge is freely selected by the user.

Figure 1 schematic diagram of fm31256
2 fm31256 functions and usage
In fm31256, there are 25 special function registers (SFR) 00h ~ 18 h. You can perform operations on these function registers to implement various functions.
2.1 Special Function registers
(1) Real-time clock and comparator
Real-time clock includes crystal oscillator, clock divider, and register system. It separates the time base signal of 32.768hz to provide 1 s (1Hz) Resolution, register (02h ~ 08 h) the second, minute, hour, week, day, month, and year information is provided in BCD format. Users can read/write the information. Before starting the clock, you must set the oscen bit (D7) of the 01h address in SFr to enable the oscillator, and set the r bit (D0) of the 00h address to the position, the clock data can be written into registers for reading. If it is in the clock refresh phase, the refresh operation takes precedence over the write register operation, thus ensuring the accuracy of the clock. When you reset the clock, you only need to set the W Bit of the H address.
The clock accuracy of fm31256 can be calibrated by software, and the Cal bit (D2) of the H address can be set, the clock enters the CALIBRATION mode, and the comparator outputs the frequency signal of Hz, you can also set the 01h address's cal4 ~ Cal0 bits (D4 ~ D0) determine the calibration value. When the Cal bit (D2) of the H address is 0, the system enters the comparator mode.
(2) Processor Companion
The Processor Companion includes the features that are commonly required by the CPU. The system monitors the interrupt output signal from the low-level status or the watchdog count overflow.
When the system power supply voltage falls below the set threshold or the watchdog counter overflows, fm31256 will output a low-level reset pulse, and the reset signal will last for 100 ms. Change the vtp1 ~ of the 0bh address ~ Vtp0 bit (d1 ~ D0), you can set the level detection threshold; change the 0ah address wdt4 ~ Wdt0 bit (D4 ~ D0), the overflow time of the watchdog can be selected from MS to 3 s, where the Wde bit of the 0ah address (D7) is used to start or stop the watchdog; the 09h address is used to monitor the reset signal source (watchdog counter, power-on reset, or backup power supply voltage) and to control the reset of the watchdog counter. The system software must be directed to the wr3 ~ Wr0 bits (D3 ~ D0) writes 1010 to clear the counter.
(3) event counters
Fm31256 has two independent backup batteries supporting 16-bit event counters Cn1 and cn2, located in registers 0dh ~ 10 h. If you set the CC bit (D2) of the 0ch address in SFr to a 32-bit counter. Cin1 and cin2 are input signals of event counters. cin2 is invalid in 32-bit counter mode. The count is triggered by Programmable edge. If the c1p bit (D0) of the 0ch address is set, cin1 is triggered by the rising edge; otherwise, it is triggered by the falling edge; c2p bit (D1) of the 0ch address) used to control cin2.
(4) Serial Data Identification Area
11h ~ in SFR of fm31256 ~ 8-byte (64-bit) data can be stored in the serial ID area of the 18 h address. This storage area is a non-volatile storage area that can perform unlimited read/write operations on it. However, if you set the SNL bit (D7) of the 0bh address, you can no longer perform operations on the bucket, and such operations are irreversible.
2.2 read/write operations on fm31256
As a slave machine, fm31256 integrates two components with different functions, each of which can be accessed independently. One is memory, and the location of the slave address during access is 7 ~ 4 must be set to 1010b. If you want to access the real-time clock/Processor Companion, then the slave address is 7 ~ 4. It must be set to 1101b. The device uses two-wire I2C interface, and the second-line protocol is determined by the status of the SDA and SCL pins. There are four statuses: start, stop, data transmission, and response. The basic communication format is 2.

Figure 2 Basic I2C bus communication format
Fm31256 operates strictly according to the time sequence and data format of the I2C bus. The access procedure can be described as follows:
Start-slave address-answer-target address-answer-(START-slave address-answer)-data (single or multi-byte)-answer-stop (note: the slave address contains the read and write commands, and the steps in the brackets are specific to the current address read and the continuous address read commands ). The response signal is described here. The response pulse occurs after 8th data bits are transmitted. In this status, the sender must release the SDA to drive the receiver. When the receiver sends a low power, it indicates a normal response. When the receiver sends a high power, it indicates no response. There are two scenarios for not responding:
First, an error occurs during data transmission. If no response is received, the sender terminates the current operation to facilitate re-Addressing. Second, the receiver intentionally does not respond to the operation to end the current operation.
When operating on SFR, the First Command byte sent is "1 1 0 1 x A1 A0 R/W", and the destination address is in the single byte range (00h ~ 18 h ). The 32kb storage unit address of fm31256 is 127h ~ 7 fffh: When operating on it, the first command byte sent is "1 0 1 0 x A1 A0 R/W", and the destination address length is double byte, that is, the addressing capability of the ram zone is 0 ~ 65
535. The fm31 series memory has the internal address lock and automatic accumulation function. When performing read/write operations on the continuous address area, you only need to send the first address of the storage area.
3 Application of fm31256 in electromagnetic casting and rolling power supply control
The fm31256 is applied to the electromagnetic casting and rolling power control device to realize the function of resetting the guard dog, setting parameters, real-time clock, and saving fault records of the main control system.
As an effective way to solve the problem that the microprocessor crashes due to interference, the role of the watchdog is essential. For control objects, three-phase control devices A, B, and C must be adjusted, this includes setting the frequency and amplitude, feedback coefficient, PID parameter, overcurrent delay, open delay, and shutdown delay of the sine wave. These parameters are promptly written into the storage unit of the fms31256, it can still be saved after power loss. When the system fails, for example, if the temperature around the thyristor in the control device exceeds the rated temperature, the device will send an alarm signal, the accurate time and actual temperature of the fault are recorded in the storage unit of fm31256 for system query. At the same time, the event counter of fm31256 is added with 1 count. Similarly, the serial identification area locking function can be used to write the serial number of the electromagnetic casting and rolling power control device into it, which is safe and reliable.
3.1 Hardware principles
The hardware interface circuit 3 of fm31256 is applied to the electromagnetic casting and rolling power supply control device. As shown in figure 3, the system uses the ultra-low power MSP430 chip msp430f149 as the controller, fm31256 as the parameter storage unit, and I2C bus is used to communicate with the processor. Because msp430f149 does not have an I2C bus interface, two I/O ports are used for simulation. The real-time clock automatically switches to the backup power supply vbak after VDD power loss.

Figure 3 hardware interface circuit of fm31256 and msp430f149
The 32.768 kHz crystal oscillator is equivalent to the 6pf capacitor. If the oscen bit corresponding to the 01h unit of SFR is set to 0 and the Cal bit of the 00h unit is set to 1, the Cal pin outputs a pulse signal of Hz, it can detect whether the crystal oscillator works normally, because 512
Hz is the 64-bit frequency of the crystal oscillator. Note the following when making PCB:
The X1 and X2 crystal oscillator pins are high-impedance pins, and the distance between the two pins must be less than 5mm. Even if the signal is located in the inner layer of the Board, the signal line is not allowed to be close to the X1 and X2 pins. Use a grounding protection ring around the crystal oscillator pin, and use a grounding protection ring inside or on the opposite side of the board to apply copper.

3.2 storage area Access Program Design
During access to the fm31256 memory, the microprocessor is in the host status, and the device is always in the slave status. According to the above analysis of fm31256, all communication processes can be classified into three types:
① Single Pulse, such as start, stop, ack, and Nack; ② byte transmission, such as transmitting data from the host address, target address, and data; ③ byte reception, such as data transmission in read operations. Therefore, as long as these operations are compiled in the form of subprograms, all communication operations can be completed by calling these subprograms. This is written in the embedded C language of msp430f149 microprocessor. Set the microprocessor port p6.6 to the data cable (SDA), and p5.4 to the clock line (SCL ).
This article does not provide a detailed description. It only provides some C language programs that simulate the I2C bus and write and read Bytes:
# Definertc_sdabit6
# Definertc_sclbit4
Void fm31256_start (void) {/* fm31256 start the program */
P6out | = rtc_sda; // SDA = 1
P5out | = rtc_scl; // SCL = 1
Delay (iic_delay );
P6out & = ~ Rtc_sda; // SDA = 0
Delay (iic_delay );
P5out & = ~ Rtc_scl; // SCL = 0}
Void fm31256_stop (void) {/* fm31256 stop the program */
P6out & = ~ Rtc_sda; // SDA = 0
Delay (iic_delay );
P5out | = rtc_scl; // SCL = 1
Delay (iic_delay );
P6out | = rtc_sda; // SDA = 1
Delay (iic_delay );}
Void fm31256_send_ack (void) {/* fm31256 Response Program */
P5out & = ~ Rtc_scl; // check the value of this parameter. The value of this parameter is 0.
P6out & = ~ Rtc_sda; // SDA = 0
P5out | = rtc_scl; // SCL = 1
Delay (iic_delay );
P5out & = ~ Rtc_scl; // SCL = 0}
Void fm31256_send_noack (void) {/* fm31256 No Response Program */
P5out | = rtc_scl; // SCL = 1
Delay (iic_delay );
P5out & = ~ Rtc_scl; // SCL = 0}
Note: The check box is displayed when the SDA line is switched from high to low, indicating the starting condition. When the check box is high, the SDA line switches from low to high, indicating that the condition is stopped. The related validation clock pulse is generated by the host, and the sender of the validation clock pulse device releases SDA (high level), during which the receiver shall lower the SDA.
Void fm31256_transfbyte_to_iic (unsigned char tran_byte ){/*
CPU byte sending program */
Unsigned char I, current_bit = 0x80;
P5out & = ~ Rtc_scl;
Delay (iic_delay );
For (I = 0; I <= 7; I ++ ){
If (tran_byte & current_bit)
P6out | = rtc_sda;
Else
P6out & = ~ Rtc_sda;
Current_bit> = 1;
Delay (iic_delay );
P5out | = rtc_scl; // SCL = 1
Delay (iic_delay );
P5out & = ~ Rtc_scl; // check the value of this parameter. The value of this parameter is 0.
Delay (iic_delay );
}
}
Unsigned char fm31256_recebyte_from_iic (void) {/* CPU byte receiving Program */
Unsigned char mvalue, I, rece_data = 0;
P6dir & = ~ Rtc_sda; // set it to the input direction.
P5out & = ~ Rtc_scl; // check the value of this parameter. The value of this parameter is 0.
Delay (iic_delay );
For (I = 0; I <8; I ++ ){
Rece_data = rece_data <1;
P5out | = rtc_scl; // SCL = 1
Delay (iic_delay );
Mvalue = p6in & rtc_sda; // the value of the current BIT
If (mvalue) // The receiving bit is high.
Rece_data = rece_data | 0x01;
Else // The receiving bit is low.
Rece_data = rece_data & 0xfe;
P5out & = ~ Rtc_scl; // check the value of this parameter. The value of this parameter is 0.
Delay (iic_delay );
}
P6dir | = rtc_sda; // p6.6 output
Return (rece_data); // return the received bytes
}
Note: Each byte sent to the SDA line must be 8 bits. Tran_byte is the byte sent by the CPU. The data read by the CPU is stored in rece_data. For fm31256 memory, you can directly perform "read" operations on the current address, or "read/write" multiple bytes consecutively without specifying the address one by one. According to the above general steps, access to the memory can be classified into three basic operations:
① Set the target address of the current operation; ② write data; ③ read data.
There are many types of access memory operations, such as memory "write", current address or sequential "read" and random address "read" operations. In the control program, data such as specified parameters and fault information needs to be written to the fm31256 memory. The memory read/write method is as follows:
For memory write operations, the CPU sends the slave address first, and then the 16-bit memory address. The host declares a write operation by setting the slave address byte to 0. After receiving the response signal, the CPU sends each byte of data to fm31256, and then the device generates a response signal. Any number of consecutive bytes can be written to stop the signal from transmitting. There are two types of read operations: Current address read operations and random address read operations. The read operation also sends the slave address by the CPU. The host declares a read operation by setting the slave address byte to 1. To perform a random read operation, you must read any byte after sending a 16-bit memory address before reading the data. After each byte, follow the response signal to stop the signal.
In the main control program of the electromagnetic casting and rolling power control device, the call clock refresh function flash_time (), the clock write function write_time (), and the Register write function register_write () are also called () and register READ function register_read ().
The flowchart 4 shows how to start RTC and watchdog.

Figure 4 flowchart for starting RTC and watchdog
Conclusion
The use of the ferrite memory in the electromagnetic casting and rolling power control device, combined with the MSP430 Series single chip microcomputer, gives full play to its powerful functions, while replacing the traditional EEPROM and real-time clock chip, it not only reduces hardware costs, but also simplifies software design. Practice has proved that fm31256 has a good prospect for promotion and application.