I2S bus Overview

The collection, processing and transmission of audio data is an important part of multimedia technology. Many digital audio systems have entered the consumer market, such as digital audio tapes and digital audio processors. For devices and manufacturers, the standardized information transmission structure can improve the adaptability of the system. The I2S (Inter-IC Sound) bus is a bus standard developed by Philips for the transmission of audio data between digital audio devices. It is dedicated to data transmission between audio devices, it is widely used in various multimedia systems. It adopts the design of transmitting clock and data signals along independent wires. By separating data and clock signals, it avoids distortion caused by time difference, this saves you the cost of buying specialized equipment to resist audio jitter.

I2S Bus Specifications

In Phillips's I2S standard, both hardware interface specifications and digital audio data formats are defined.

I2S has three main signals

1. The serial clock sclk, also known as the Bit Clock (bclk), corresponds to each bit of data in the digital audio. sclk has one pulse. Sclk frequency = 2 × sampling frequency × number of sampling digits.

2. The frame clock lrck (also known as ws) is used to switch the data of the left and right channels. When lrck is set to "1", it indicates that the Left-channel data is being transmitted. If lrck is set to "0", it indicates that the right-channel data is being transmitted. The lrck frequency is equal to the sampling frequency.

3. Serial Data sdata is the audio data represented by binary complement code.

Sometimes, in order to enable better synchronization between systems, we also need to transmit another mclk signal, called the main clock, also known as the system clock, which is 256 times or 384 times the sampling frequency.

Serial Data (SD)

No matter how many bits of valid data exist, the highest bits of the data always appear at the first 2nd sclk pulses after the lrck change (that is, the beginning of a frame. This allows the receiver and the sender to have different valid digits. If the number of valid bits processed by the receiving end is less than that of the sending end, you can discard the redundant low bits in the data frame. If the number of valid bits processed by the receiving end is more than that of the sending end, you can replace the remaining bits. This synchronization mechanism makes it easier for digital audio devices to interconnect with each other without causing data misplacement.

With the development of technology, a variety of different data formats have emerged under the unified I2S interface. Sdata is divided into left alignment (rarely used), I2S format (specified by Philips), and right alignment (also called Japanese format and common format) based on the location of sdata data relative to lrck and sclk ).

To ensure the correct transmission of digital audio signals, the sender and receiver must adopt the same data format and length. Of course, for I2S format, the data length can be different.

Field (audio channel) selection (WS)

Command selection line indicates the channel being transmitted.

Ws = 1, indicating that the Left-channel data is being transmitted.

Ws = 0 indicates that data in the right channel is being transmitted.

WS can change the rising or falling edge of the serial clock, and WS signals do not need to be symmetric. On the slave device side, WS change along the rising edge of the clock signal. WS always changes the clock period before the highest bit transmission, so that the slave device can synchronize time with the transmitted serial data, in addition, the receiver stores the current command and clears the space for the next command.

Electrical specifications:

Output voltage:

Vl <0.4 V

Vl> 2.4 V

Input voltage

Devil = 0.8 V

VIH = 2.0 V

Note: currently, TTL level standards are used. With the prevalence of other IC (LSI), other levels are also supported.

Timing requirements:

In the I2S bus, any device can become the dominant device of the system by providing the necessary clock signal, and the subordinate device obtains its internal clock signal through the external clock signal, this means that the propagation delay between the dominant device and data and the command selection signal must be emphasized. The total delay is mainly composed of two parts:

1. latency between the external clock and the internal clock of the Slave Device

2. latency between internal clock and data signals and command selection signals

For data and command signal input, the latency of the external clock and internal clock is not dominant, but it only prolongs the effective set-up time ). The main part of latency is the transmission latency of the sender and the time required to set the receiver.

T is the clock cycle, TR is the minimum allowed clock cycle, T> tr so that the sender and receiver can meet the data transmission rate requirements.

For all data rates, both the sender and acceptor send a clock signal with a fixed sign-space ratio, therefore, t LC and THC are defined by T. T LC and thc must be greater than 0.35 T, so that the signal can be detected at the slave device side.

Latency (tdtr) is related to the fastest transmission speed (defined by TTR). A slow rising speed of the sending end signal may cause the tdtr to not exceed the TRC and cause the thtr to be zero or negative. Only when TRC is not greater than trcmax (trcmax>: 0.15 t) Can the sender ensure that thtr is greater than or equal to 0.

In order to allow the data to be recorded at the descent edge, the rising edge of the clock signal and the T-related time delay should be given to the receiver with sufficient set-up time ).

The set-up time and hold time cannot be less than the set-up time and hold time of the specified acceptor.

I2S Bus Structure Configuration

As ws signal changes, a WSP pulse signal is exported to the parallel shift register, and the output data is activated. The default input value of serial data is 0, so all data after the LSB is set to 0.

As the first ws signal changes, WSP resets the counter along the descent of the sck signal. After the "1 out of N" decoder decodes counter values, the first serial data (MSB) is stored in B1 on the rising edge of the sck clock signal. As the counter grows, the subsequent data is stored in B2. When the next ws signal changes, the data is stored in the left (Channel) or right (Channel) latches based on the changes in the WSP pulse, in addition, the b2-bn data is cleared and the counter is reset. If redundant data exists, the data after the percentile is ignored. Note: The decoder and counter (in the dotted line) can be replaced by an N-bit shift register.

The IIS bus interface can be used as an encoding and decoding interface to connect to the external 8/16-bit stereo audio frequency decoding circuit (codec ic) to implement micro-recording and portable applications. It supports IIS data format and MSB-justified data format. The IIS bus interface provides DMA transmission mode to replace the interrupt mode for first-in-first-out queue FIFO access. It can send and receive data at the same time or only send or receive data.