I2S Audio bus Learning (2) I2S bus protocol

I2S Audio bus Learning (2) I2S Bus Protocol I. I2S bus Overview

The collection, processing and transmission of audio data is an important part of multimedia technology. Many digital audio systems have entered the consumer market, such as digital audio tapes and digital audio processors. For devices and manufacturers, the standardized information transmission structure can improve the adaptability of the system. The I2S (Inter-IC Sound) bus is a bus standard developed by Philips for the transmission of audio data between digital audio devices. It is dedicated to data transmission between audio devices, it is widely used in various multimedia systems.

Ii. I2S Bus Specifications

The I2S bus has three data signal lines:

1. sck: (continuous serial clock) serial clock

The sck has one pulse for each bit of digital audio. Sck frequency = 2 × sampling frequency × number of sampling digits.

2. WS: (word select) field (audio channel) Selection

Used to switch the data of the left-right channel. WS frequency = sampling frequency. Command selection line indicates the channel being transmitted.
If ws is set to "1", the left-channel data is being transmitted.
If ws is set to "0", data in the right channel is being transmitted.
WS can change the rising or falling edge of the serial clock, and WS signals do not need to be symmetric. On the slave device side, WS change along the rising edge of the clock signal. WS always changes the clock period before the highest bit transmission, so that the slave device can synchronize time with the transmitted serial data, in addition, the receiver stores the current command and clears the space for the next command.

3. SD: (Serial Data) Serial Data

Audio Data in binary complement representation. No matter how many bits of valid data exist, the highest bits of the data are always transmitted first (at the first 2nd sck pulses after the WS change (that is, the beginning of a frame ), therefore, the highest bit has a fixed position, while the second bit is dependent on the valid digits of the data. In this way, the number of valid digits between the receiver and the sender can be different. If the receiving end can process less than the sending end, it can discard the redundant low-level data in the data frame. If the receiving end can process more than the sending end, you can manually fill in the remaining bits (usually zero complement ). This synchronization mechanism makes it easier for digital audio devices to interconnect with each other without causing data misplacement. To ensure the correct transmission of digital audio signals, the sender and receiver must adopt the same data format and length. Of course, for I2S format, the data length can be different.
For the system, the signal end that generates sck and WS is the master device, represented by the master, as shown in simple system 1:

Figure 1 simple system configuration and basic interface timing


See figure 2 for the timing diagram of another basic interface:

Figure 2 I2S typical interface Time Series
4. timing requirements in IIS Bus, any device can become the main device of the system by providing the necessary clock signal, and the subordinate device obtains its internal clock signal through the external clock signal, this means that the transmission delay between the master device and the data and the command selection signal must be emphasized. The total delay is mainly composed of two parts:
1. latency between the external clock and the internal clock of the Slave Device
2. latency between internal clock and data signals and command selection signals
For data and command signal input, the latency of the external clock and internal time is not dominant, but it only prolongs the effective set-up time ). The main part of latency is the transmission latency of the sender and the time required to set the receiver. See figure 3 and figure 4:

Figure 3 timing for IIS Transmitter
Figure 4 timing for IIS Explorer:

5. Electrical Characteristics

Output voltage:

Vl <0.4 V
Vl> 2.4 V

Input voltage

Devil = 0.8 V
VIH = 2.0 V

Note: currently, TTL level standards are used. With the prevalence of other IC (LSI), other levels are also supported.